Analysis of Testing Techniques for Low Power Applications

Authors

  • M. PavithraJyothi  Research Scholar ,SUNRISE University, Alwar, Rajasthan, India
  • Dr. C. Ramsingla  Professor, Department of ECE, SUNRISE University, Alwar, Rajasthan, India

Keywords:

Test Pattern, X-Filling, Arithmetic Coding, Genetic Algorithms, Built, Self-Test.

Abstract

Power consumption during test has become an important role in test manufacturing because it can lead to the destructive testing and some time the problem of wrong response due to overheating, so reducing power is a main objective during circuit design. This paper proposes comparison of results of the existing techniques. New techniques can be proposed in the future to reduce more power without any compromise.

References

  1. Abramovici, M.; Breuer, M.; Friedman, A, "Digital Systems Testing and Testable Design", Wiley-IEEE Press, 1990
  2. Patrick Girard, Nicola Nicolici, Xiaoqing Wen, "Power Aware Testing and Test Strategies for Low Power Devices", Springer Science Business Media, 2010
  3. Patrick Girard, "Low Power Testing of VLSI Circuits: Problems and Solutions", Quality Electronic Design, IEEE 2000 First International Symposium on March 2000
  4. Chul-ki Baek, Insoo Kim, Jung-Tae Kim, Yong-Hyun Kim, Hyoung Bok Min, and Jae-Hoon Lee, "A Dynamic Scan Chain Reordering for Low-Power VLSI Testing", Information Technology Convergence and Services (ITCS), 2nd International Conference on August 2010
  5. Samah Mohamed Saeed, Ozgur Sinanoglu,and Sobeeh Almukhaizim, "Predictive Techniques for Projecting Test Data Volume Compression", IEEE transactions on very large scale integration systems, vol. 21, no. 9, September 2013
  6. Sudip Roy, Indranil Sen Gupta and Ajit Pal, "Artificial Intelligence Approach to Test Vector Reordering for Dynamic Power Reduction during VLSI Testing", TENCON, IEEE Region 10 Conference, November 2008
  7. H. Hashempour and F. Lombardi, "Compression of VLSI Test Data by Arithmetic Coding", Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004. Proceedings. 19th IEEE International Symposium on 10-13 Oct. 2004
  8. P.Basker & A.Arulmurugan, "Survey of Low Power Testing of VLSI Circuits", International Conference on Computer Communication and Informatics (ICCCI-2012), Jan. 10 – 12, 2012
  9. Peter Wohl, John A. Waicukauski, Frederic Neuveux, Emil Gizdarski, "Fully X-tolerant, Very High Scan Compression", Design Automation Conference (DAC), 2010 47th ACM/IEEE
  10. Walid Ibrahim, Amr Elchouemi, and Hoda Amer, "A Two-Phase Genetic Algorithm for VLSI Test vector Selection", IEEE Congress on Evolutionary Computation, July 2006
  11. Po-Han Wu, Tsung-Tang Chen, Wei-Lin Li and Jiann- Chyi Rau, "An Efficient Test-Data Compaction for Low Power VLSI Testing", Electro/Information Technology, IEEE International Conference on May2008.

International Journal of Scientific Research in Science, Engineering and Technology

Downloads

Published

2016-12-30

Issue

Volume 2, Issue 6, November-December-2016

Section

Research Articles

License

Copyright (c) IJSRSET

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
M. PavithraJyothi, Dr. C. Ramsingla, " Analysis of Testing Techniques for Low Power Applications, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 6, pp.766-769, November-December-2016.