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Implementation of Self-Checking Carry-Select Adder Based on Two-Rail Encoding in FPGA

Authors(2):

G. Naresh, P. Praveenkumar
  • Abstract
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Self-checking carry-select adder design based on two-rail encoding is an efficient method, due to its arithmetic operations and short delay. This paper presents the design of the Compressor based Self-checking carry-select adder design .The circuit can detect all single stuck-at faults during on-line operation mode. Its performance is increased by using compressor by replacing all full adders.

G. Naresh, P. Praveenkumar

Compressor, carry select Adder, Area, Delay, Area-Delay Product.

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  2. D. P. Vasudevan, P. K. Lala, and J. P. Parkerson, "Self-checking carry select adder design based on two-rail encoding," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 12, pp. 2696-2705, Dec. 2007.
  3. Hamdi Belgacem, Khedhiri Chiraz and Tourki Rached, "A novel differential XOR-based self-checking adder", Vol. 99, No. 9, September 2012, 1239-1261.
  4. Sanjeev Kumar and Manoj Kumar, "Low Power High Speed 3-2 Compressor" International journal of Electrical, Electronic and Mechanical controls ISSN (online): 2319-7509

Publication Details

Published in : Volume 1 | Issue 4 | July-August - 2015
Date of Publication Print ISSN Online ISSN
2015-08-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
412-414 IJSRSET151480   Technoscience Academy

Cite This Article

G. Naresh, P. Praveenkumar, "Implementation of Self-Checking Carry-Select Adder Based on Two-Rail Encoding in FPGA", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 4, pp.412-414, July-August-2015.
URL : http://ijsrset.com/IJSRSET151480.php

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