This work represents implementation of UART (universal asynchronous receiver transmitter with the error correction and detection capability of one bit with different frame of bits. But the frame of bits should be equal to four bits and can be up to eight bits. In this phenomenon two operating modes can be used in application by the design circuit configuration, first is the normal mode in which one parity bit is added for one bit error detection and the second mode is error correction where single error can be corrected and double error can be detected. By use of this work there is no need of built-in-self test. The error correction used in this design is extended hamming code in which four numbers of hamming bits are added for error correction capability mode. In this configuration the baud rate of transmission and reception can be selected dynamically amongst eight different options. This design configuration is implemented on Field programmable gate array (FPGA), and the target device is Spartan 3E.
Amit Khare, Nitesh Dodkey
UART, FPGA, Forward Error Correction, Error detection, Baud Rate
- R. W. Hamming, “Error detecting and error correcting codes”, The Bell System Technical journal Vol. XXIX, April 1950, Vol. 2, American Telephone and Telegraph company.
- Naresh Patel, Vatsalkumar Patel, Vikaskumar Patel, ”VHDL Implementation of UART with Status Register”, 2012 IEEE International Conference on Communication Systems and Network Technologies, 2012.
- Elmenreich W, Delvai M, "Time-triggered communication with UARTs”, 4thIEEE International Workshop on Factory Communication Systems, 2002, pp. 97- 104, 2002.
- Gallo R, Delvai M, Elmenreich W, Steininger A, “Revision and verification of an enhanced UART”, 2004, Proceedings, 2004 IEEE International Workshop on Factory Communication Systems, pp. 315- 318, 22-24, Sept. 2004.
- Norhuzaimin J, Maimun H.H, "The design of high speed UART", Asia- Pacific Conference on Applied Electromagnetics (APACE), pp. 20- 21, Dec. 2005.
- Fang Yi-yuan, Chen Xue-jun, "Design and Simulation of UART Serial Communication Module Based on VHDL", 2011 3rd International Workshop on Intelligent Systems and Applications (ISA), pp. 1-4, 28- 29, May 2011. Yongcheng Wang, Kefei Song, "A new approach to realize UART", 2011 International Conference on Electronic and Mechanical Engineering and Information Technology (EMEIT), pp. 2749-2752, 2011.
- Himanshu Patel, Sanjay Trivedi, R. Neelkanthan, V. R. Gujraty , "A Robust UART Architecture Based on Recursive Running Sum Filter for Better Noise Performance", Held jointly with 6th International Conference on Embedded Systems, 20th International Conference on VLSI Design, pp. 819-823, Jan. 2007.
- Idris, M.Y.I, Yaacob M, "A VHDL implementation of BIST technique in UART design", 2003 Conference on Convergent Technologies for Asia-Pacific Region (TENCON), pp. 1450-1454, 2003.
- Chun-zhi He, Yin-shui Xia, Lun-yao, Wang, "A universal asynchronous receiver transmitter design”, 2011 International Conference on Electronics Communications and Control (ICECC), pp. 691-694, 9-11, Sept. 2011.
- Prof. Rami Abielmona, “Project UART Design”, for CEG 3150, Digital Systems-II, Fall 2004, November 24, 2004.
|Published in :
||Volume 1 | Issue 6 | November-December - 2015
|Date of Publication
Cite This Article
Amit Khare, Nitesh Dodkey, "Implementation of UART with Error Correction and Error Detection Capability & Frame Length Selection", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 6, pp.275-280, November-December-2015.
URL : http://ijsrset.com/IJSRSET151648.php