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Implementation of UART with Error Correction and Error Detection Capability & Frame Length Selection

Authors(2):

Amit Khare, Nitesh Dodkey
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This work represents implementation of UART (universal asynchronous receiver transmitter with the error correction and detection capability of one bit with different frame of bits. But the frame of bits should be equal to four bits and can be up to eight bits. In this phenomenon two operating modes can be used in application by the design circuit configuration, first is the normal mode in which one parity bit is added for one bit error detection and the second mode is error correction where single error can be corrected and double error can be detected. By use of this work there is no need of built-in-self test. The error correction used in this design is extended hamming code in which four numbers of hamming bits are added for error correction capability mode. In this configuration the baud rate of transmission and reception can be selected dynamically amongst eight different options. This design configuration is implemented on Field programmable gate array (FPGA), and the target device is Spartan 3E.

Amit Khare, Nitesh Dodkey

UART, FPGA, Forward Error Correction, Error detection, Baud Rate

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Publication Details

Published in : Volume 1 | Issue 6 | November-December - 2015
Date of Publication Print ISSN Online ISSN
2015-12-25 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
275-280 IJSRSET151648   Technoscience Academy

Cite This Article

Amit Khare, Nitesh Dodkey, "Implementation of UART with Error Correction and Error Detection Capability & Frame Length Selection", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 6, pp.275-280, November-December-2015.
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