Implementation of Optimized Floating Point Arithmetic Unit on Reconfigurable Logic

Authors(2) :-Sonam Pardhi, Nitesh Dodkey

This paper presents the FPGA implementation of a Decimal Floating Point (DFP) arithmetic unit. The design performs addition, subtraction and multiplication on 64-bit operands that use the IEEE 754-2008 DPD encoding of DFP numbers. The design uses an equal bypass adder, this adder reduces the power consumption and it also reduces the delay by reducing the gate count. The design also uses barrel shifter instead of sequential shifter to reduce delay. Also 64 bit parallel BCD multiplier is used to perform fixed point multiplication. The proposed DFP arithmetic unit supports operations on the decimal64 format and it is easily extendable for the decimal128 format.

Authors and Affiliations

Sonam Pardhi
Department of Electronics and Communication Engineering, Surbhi group of Institute, Madhya Pradesh, India
Nitesh Dodkey
Department of Electronics and Communication Engineering, Surbhi group of Institute, Madhya Pradesh, India

Floating point addition, Floating point multiplication, Floating point subtraction, FPGA, Delay, Area overhead, IEEE P754-2008

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Publication Details

Published in : Volume 1 | Issue 6 | November-December 2015
Date of Publication : 2015-12-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 340-347
Manuscript Number : IJSRSET151678
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Sonam Pardhi, Nitesh Dodkey, " Implementation of Optimized Floating Point Arithmetic Unit on Reconfigurable Logic, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 6, pp.340-347, November-December-2015.
Journal URL : http://ijsrset.com/IJSRSET151678

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