Hardware & Power efficient Multiplier

Authors

  • Geetanjali Sharma  Department of Electronics and Telecommunication, Surabhi Group of Institution, Madhya Pradesh, India
  • Nitesh Dodkey  Department of Electronics and Telecommunication, Surabhi Group of Institution, Madhya Pradesh, India

Keywords:

Power Efficient, Multiplier, Switching Delay, Hardware Efficient and Resource Reuse

Abstract

This paper presents a hardware and power efficient binary multiplier using resource reuse technique. The proposed design uses efficient design of half and full adder circuits which uses less number of logic gates. An array multiplier of n x n needs n rows and n columns of full adder circuits to generate the product term. The proposed design requires only 3 rows of adders to generate the product term. Intermediate product terms are stored in the memory elements (flip flop). As flip flops takes less area and consume less power as compared to adder circuit (combinational circuit), this improves the hardware efficiency and power efficiency of the design. This technique is used to implement a 8 x 8 multiplier and the results are compared with other 8 x 8 array multipliers. Spartan 3 FPGA is used to implement the design. The design is very linear and it can be easily extended to implement large multiplier.

References

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2015-12-30

Issue

Volume 1, Issue 6, November-December-2015

Section

Research Articles

License

Copyright (c) IJSRSET

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Geetanjali Sharma, Nitesh Dodkey, " Hardware & Power efficient Multiplier, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 6, pp.352-357, November-December-2015.