Design of Delay Lock Loop with Dual Control Using LT-Spice

Authors(5) :-K. Ragupathi, J. Imran Khan, M. Karthik, S. Rajan, D.Vignesh kumar

The paper presents A CMOS Delay Lock Loop with Dual Control. Positron emission tomography (PET) with time-of-flight (TOF) capability has been shown to provide a better reconstructed image compared to conventional positron tomography. Resolution is the biggest problem in PET. To achieve such resolution, time interpolations and multiphase sampling techniques are the mostly used methods. A precise multiphase clock generator should be required. Generally, the timing generator is realized by using a delay-locked loop (DLL) due to its good performances on low jitter and easier integration implemented in CMOS process.

Authors and Affiliations

K. Ragupathi
Department of ECE, Velammal Institute of Technology, Chennai, Tamilnadu, India
J. Imran Khan
Department of ECE, Velammal Institute of Technology, Chennai, Tamilnadu, India
M. Karthik
Department of ECE, Velammal Institute of Technology, Chennai, Tamilnadu, India
S. Rajan
Department of ECE, Velammal Institute of Technology, Chennai, Tamilnadu, India
D.Vignesh kumar

CMOS, time-of-flight, delay-locked loop, Positron emission tomography, CDR, VCDL, LPF

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Publication Details

Published in : Volume 1 | Issue 2 | March-April 2015
Date of Publication : 2015-04-25
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 329-333
Manuscript Number : IJSRSET1522110
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

K. Ragupathi, J. Imran Khan, M. Karthik, S. Rajan, D.Vignesh kumar, " Design of Delay Lock Loop with Dual Control Using LT-Spice, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 2, pp.329-333, March-April-2015.
Journal URL : http://ijsrset.com/IJSRSET1522110

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