The paper presents “A CMOS Delay Lock Loop with Dual Control”. Positron emission tomography (PET) with time-of-flight (TOF) capability has been shown to provide a better reconstructed image compared to conventional positron tomography. Resolution is the biggest problem in PET. To achieve such resolution, time interpolations and multiphase sampling techniques are the mostly used methods. A precise multiphase clock generator should be required. Generally, the timing generator is realized by using a delay-locked loop (DLL) due to its good performances on low jitter and easier integration implemented in CMOS process.
K. Ragupathi, J. Imran Khan, M. Karthik, S. Rajan, D.Vignesh kumar
CMOS, time-of-flight, delay-locked loop, Positron emission tomography, CDR, VCDL, LPF
' F. M. Gardner, "Charge-pump phase-lock loops, " IEEE Trans. Commun., vol. COM 28, pp. 1849-1858, Nov. 1980.
 B. Razavi, "Phase-locking in high-performance systems: from devices to architectures, " John Wiley & Sons, Inc. 2003.
 R. B. Watson Jr. and R. B. Iknaian, "Clock buffer chip with multiple target automatic skew compensation, " IEEE J. Solid-State Circuits, vol. 30, pp. 1267-1276, Nov. 1995.
 C. H. Kim et al., "A 64-Mbit 640-Mbyte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-Mbyte memory system, " IEEE J. Solid-State Circuits, vol. 33, pp. 1703-1710, Nov. 1998.
 Y. Moon et al., "An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performance, " IEEE J. Solid-State Circuits, vol. 35, pp. 377-384, Mar. 2000.
 H. H. Chang et al., "A wide-range delay-locked loop with a fixed latency of one clock cycle, " IEEE J. Solid-State Circuits, vol. 37, pp. 1021-1027, Aug. 2002.
 S. Sidiropoulos, "High-performance inter-chip signalling, " Ph.D. Dissertation, Stanford University, 1998.
 M. J. E. Lee, "An efficient I/O and clock recovery design for terabit integrated circuits, " Ph.D. dissertation, Stanford University, 2002.
 D. J. Foley and M. P. Flynn, "CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator, " IEEE J. Solid-State Circuits, vol. 36, pp. 417-423, Mar. 2001.
 C. Kim, I. C. Hwang, and S. M. Kang, "Low-power small area +-7.28ps jitter 1GHz DLL-based clock generator, " IEEE J. Solid-State Circuits, vol. 37, pp. 1414-1420, Nov. 2002.'
|Published in :
||Volume 1 | Issue 2 | March-April - 2015
|Date of Publication
Cite This Article
K. Ragupathi, J. Imran Khan, M. Karthik, S. Rajan, D.Vignesh kumar, "Design of Delay Lock Loop with Dual Control Using LT-Spice", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 2, pp.329-333, March-April-2015.
URL : http://ijsrset.com/IJSRSET1522110.php