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Design of Delay Lock Loop with Dual Control Using LT-Spice

Authors(5):

K. Ragupathi, J. Imran Khan, M. Karthik, S. Rajan, D.Vignesh kumar
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The paper presents “A CMOS Delay Lock Loop with Dual Control”. Positron emission tomography (PET) with time-of-flight (TOF) capability has been shown to provide a better reconstructed image compared to conventional positron tomography. Resolution is the biggest problem in PET. To achieve such resolution, time interpolations and multiphase sampling techniques are the mostly used methods. A precise multiphase clock generator should be required. Generally, the timing generator is realized by using a delay-locked loop (DLL) due to its good performances on low jitter and easier integration implemented in CMOS process.

K. Ragupathi, J. Imran Khan, M. Karthik, S. Rajan, D.Vignesh kumar

CMOS, time-of-flight, delay-locked loop, Positron emission tomography, CDR, VCDL, LPF

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Publication Details

Published in : Volume 1 | Issue 2 | March-April - 2015
Date of Publication Print ISSN Online ISSN
2015-04-25 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
329-333 IJSRSET1522110   Technoscience Academy

Cite This Article

K. Ragupathi, J. Imran Khan, M. Karthik, S. Rajan, D.Vignesh kumar, "Design of Delay Lock Loop with Dual Control Using LT-Spice", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 2, pp.329-333, March-April-2015.
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