Packet Prediction Circuitry to Reduce Latency and Power Using OpenFlow Switches

Authors(3) :-Adhirai B, Akshaya K, P Prema

The Ethernet switch is a major building block. For today’s enterprise networks and data centers. As network technologies congregate ahead a single Ethernet fabric,there is enduring pressure to increae the performance and efficiency of the switch while maintaining elasticity and a well-to-do position of packet processing features. The OpenFlow architecture aims to provide elasticity and programmable packet processing to meet these converging needs. Of the several ways to generate an OpenFlow switch, a popular preference is to create deep use of ternary content addressable memories (TCAMs). Regrettably, TCAMs can consume a significant amount of power and, when used to equal flows in an OpenFlow switch, put a hurdle on switch latency. In this paper, we propose enhancing an OpenFlow Ethernet switch with per-port packet prediction circuitry in order to simultaneously reduce latency and power consumption without sacrificing rich policy-based forwarding enabled by the OpenFlow architecture. Packet prediction exploits the sequential position network communications to predict the flow arrangement of arriving packets. When predictions are correct, latency can be reduced, and considerable power savings can be achieved from bypassing the full lookup process. IP and Transport networks are controlled and operated independently today, leading to significant Capex and Opex inefficiencies for the providers. We discuss a unified approach with OpenFlow, and present a recent demonstration of a unified control plane for OpenFlow enabled IP/Ethernet networks. Imitation studies using actual network traces point out that correct prediction rates of 97% are achievable using only a small amount of prediction circuitry per port. OpenFlow is based on an Ethernet switch, with an internal flow-table, and a standardized interface to add and remove flow entries. Our goal is to encourage networking vendors to add OpenFlow to their switch products for deployment in college campus backbones and wiring closets. We believe at OpenFlow is a pragmatic compromise: on one hand, it allows researchers to run experiments on heterogeneous switches in a uniform way at line-rate and with high port-density; while on the other hand, vendors do not need to expose the internal workings of their switches

Authors and Affiliations

Adhirai B
Department of Computer Science, Dhanalakshmi College of Engineering, Chennai, Tamilnadu, India
Akshaya K
Department of Computer Science, Dhanalakshmi College of Engineering, Chennai, Tamilnadu, India
P Prema
Department of Computer Science, Dhanalakshmi College of Engineering, Chennai, Tamilnadu, India

Ethernet networks, packet switching, software defined networking.

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Publication Details

Published in : Volume 1 | Issue 2 | March-April 2015
Date of Publication : 2015-04-25
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 95-103
Manuscript Number : IJSRSET152229
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Adhirai B, Akshaya K, P Prema, " Packet Prediction Circuitry to Reduce Latency and Power Using OpenFlow Switches, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 2, pp.95-103, March-April.2015
URL : http://ijsrset.com/IJSRSET152229

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