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Packet Prediction Circuitry to Reduce Latency and Power Using OpenFlow Switches

Authors(3):

Adhirai B, Akshaya K, P Prema
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The Ethernet switch is a major building block. For today’s enterprise networks and data centers. As network technologies congregate ahead a single Ethernet fabric,there is enduring pressure to increae the performance and efficiency of the switch while maintaining elasticity and a well-to-do position of packet processing features. The OpenFlow architecture aims to provide elasticity and programmable packet processing to meet these converging needs. Of the several ways to generate an OpenFlow switch, a popular preference is to create deep use of ternary content addressable memories (TCAMs). Regrettably, TCAMs can consume a significant amount of power and, when used to equal flows in an OpenFlow switch, put a hurdle on switch latency. In this paper, we propose enhancing an OpenFlow Ethernet switch with per-port packet prediction circuitry in order to simultaneously reduce latency and power consumption without sacrificing rich policy-based forwarding enabled by the OpenFlow architecture. Packet prediction exploits the sequential position network communications to predict the flow arrangement of arriving packets. When predictions are correct, latency can be reduced, and considerable power savings can be achieved from bypassing the full lookup process. IP and Transport networks are controlled and operated independently today, leading to significant Capex and Opex inefficiencies for the providers. We discuss a unified approach with OpenFlow, and present a recent demonstration of a unified control plane for OpenFlow enabled IP/Ethernet networks. Imitation studies using actual network traces point out that correct prediction rates of 97% are achievable using only a small amount of prediction circuitry per port. OpenFlow is based on an Ethernet switch, with an internal flow-table, and a standardized interface to add and remove flow entries. Our goal is to encourage networking vendors to add OpenFlow to their switch products for deployment in college campus backbones and wiring closets. We believe at OpenFlow is a pragmatic compromise: on one hand, it allows researchers to run experiments on heterogeneous switches in a uniform way at line-rate and with high port-density; while on the other hand, vendors do not need to expose the internal workings of their switches

Adhirai B, Akshaya K, P Prema

Ethernet networks, packet switching, software defined networking.

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[1] N. McKeown, T. Anderson,H.Balakrishnan, G. Parulkar, L. Peterson, J. Rexford, S. Shenker, and J. Turner, “OpenFlow: Enabling innovation in campus networks,” Comput. Commun. Rev., vol. 38, pp. 69–74, 2008.

[2] B. Salisbury, “TCAMs and OpenFlow—What every SDN practitioner must know,” SDN Central, 2012 [Online]. Available:http://www.sdncentral.com/products-technologies /sdn-openflow-tcam-need-to-know/2012/07/

[3] B. Heller, “OpenFlow switch specification,” OpenFlow Consortium, 2008 [Online]. Available: http://www. openflowswitch.org/documents/openflow-spec-v0.8.9.pdf

[4] P. Gupta, S. Lin, and N. McKeown, “Routing lookups in hardware at memory access speeds,” in Proc. 17th Annu. IEEE INFOCOM, 1998, vol. 3, pp. 1240–1247.

[5] H. H. Y. Tzeng and T. Przygienda, “On fast address-lookup algorithms,” IEEE J. Sel. Areas Commun., vol. 17, no. 6, pp. 1067–1082, Jun. 1999.

[6] J. van Lunteren and T. Engbersen, “Fast and scalable packet           classification,” IEEE J. Sel. Areas Commun., vol. 21, no. 4, pp. 560–571, May 2003.

[7] J. Liao, “SDN system performance,” 2012 [Online]. Available: http:// pica8.org/blogs/?p=201

[8] R. Ozdag, “Intel ethernet switch FM6000 series—Software defined  neworking,” Intel Corporation, 2012, p. 8.

[9] Arista Networks, Inc., Santa Clara, CA, USA, “7150 series 1/10 GbE SFP ultra low latency switch,” 2012.

[10] Cisco Systems, Inc., San Jose, CA, USA, “Cisco Nexus 3548 switch architecture,” 2012.

[11] D. Serpanos and T. Wolf, Architecture of Network Systems. Boston,  MA, USA: Morgan Kaufmann.

[12] P. Gupta and N. McKeown, “Algorithms for packet classification,” IEEE Netw., vol. 15, no. 2, pp. 24–32, Mar. 2001, 2001.

[13] D. E. Taylor, “Survey and taxonomy of packet classification      techniques,”Comput.Surv., vol. 37, pp. 238–275, 2005.

[14] G. Nychis, C. Fallin, T. Moscibroda, and O. Mutlu, “Next generation on-chip networks: What kind of congestion control do we need?,” in Proc. 9thACM SIGCOMMWorkshopHot Topics Netw.,Monterey, CA, USA, Art. no. 12.

[15] C. Minkenberg,M. Gusat, and G. Rodriguez, “Adaptive routing in data center bridges,” in Proc. 17th IEEE HOTI, 2009, pp. 33–41.

[16] R. Jain and S. Routhier, “Packet trains-measurements and a new model for computer network traffic,” IEEE J. Sel. Areas Commun., vol. SAC-4, no. 6, pp. 986–995, Sep. 1986.

[17] C. Partridge, “Locality and route caches,” 1996 [Online]. Available: http://www.caida.org/outreach/isma/9602/positions/ partridge.html

[18] D. C. Feldmeier, “Improving gateway performance with a routing-table cache,” in Proc. 7th Annu. IEEE INFOCOM, 1988, pp. 298–307.

[19] P. Newman, G. Minshall, T. Lyon, and L. Huston, “IP switching and gigabit routers,” IEEE Commun. Mag., vol. 35, no. 1, pp. 64–69, Jan. 1997.

[20] T. Benson, A. Anand, A. Akella, and M. Zhang, “Understanding data center traffic characteristics,” in Proc. ACM SIGCOMM Workshop Enterprise  Netw., Barcelona, Spain, 2009, pp. 65–72.

[21] A. Partow, “General purpose hash function algorithms,” 2013 [Online].Available:        http://www.partow.net/programming/ hashfunctions/index.html

[22] G. Ananthanarayanan and R. H. Katz, “Greening the switch,” in Proc. USENIX Conf. Power Aware Comput. Syst., San Diego, CA, USA, 2008, p. 7.

[23] P. Mahadevan, P. Sharma, S. Banerjee, and P. Ranganathan, “A power benchmarking framework for network devices,” in Proc. NETWORKING, 2009, pp. 795–808.

[24] H.-S.Wang, L.-S. Peh, and S. Malik, “Apower model for routers:   Modeling alpha 21364 and InfiniBand routers,” IEEE Micro, vol. 23, no. 1,  pp. 26–35, Jan.–Feb. 2003.

[25] T. T. Ye, L. Benini, and G. De Micheli, “Analysis of power  consumption on switch fabrics in network routers,” in Proc. 39th Design Autom. Conf., 2002, pp. 524–529.

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Publication Details

Published in : Volume 1 | Issue 2 | March-April - 2015
Date of Publication Print ISSN Online ISSN
2015-04-25 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
95-103 IJSRSET152229   Technoscience Academy

Cite This Article

Adhirai B, Akshaya K, P Prema, "Packet Prediction Circuitry to Reduce Latency and Power Using OpenFlow Switches", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 1, Issue 2, pp.95-103, March-April-2015.
URL : http://ijsrset.com/IJSRSET152229.php

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