Implementation of Fast Fourier Transform using Resource Reuse Technique on FPGA

Authors

  • Praveen Kumar Jhariya  Department of Electronics and Communication Engineering, Surbhi Group of Institute, Madhya Pradesh, India
  • Nitesh Dodkey  Department of Electronics and Communication Engineering, Surbhi Group of Institute, Madhya Pradesh, India

Keywords:

FFT, FPGA, Hardware Reuse, Butterfly

Abstract

The utility of discrete Fourier transform (DFT) plays important role in many of digital processing including linear filtering, correlation analysis and spectrum analysis. In this work we have proposed two FFT designs, design 1 and design 2. In design 1 we have only one butterfly unit and one multiplier and this butterfly unit along with complex multiplier is used multiple times to compute the 8 point FFT. In design 2 four butterfly fly unit and two multipliers which are used 3 times. The number system used in our design is single precision (32 bit) floating point and 8 bit floating point.

References

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2016-02-25

Issue

Volume 2, Issue 1, January-February-2016

Section

Research Articles

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How to Cite

[1]
Praveen Kumar Jhariya, Nitesh Dodkey, " Implementation of Fast Fourier Transform using Resource Reuse Technique on FPGA , International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.52-58, January-February-2016.