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Implementation of Fast Fourier Transform using Resource Reuse Technique on FPGA


Praveen Kumar Jhariya, Nitesh Dodkey
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The utility of discrete Fourier transform (DFT) plays important role in many of digital processing including linear filtering, correlation analysis and spectrum analysis. In this work we have proposed two FFT designs, design 1 and design 2. In design 1 we have only one butterfly unit and one multiplier and this butterfly unit along with complex multiplier is used multiple times to compute the 8 point FFT. In design 2 four butterfly fly unit and two multipliers which are used 3 times. The number system used in our design is single precision (32 bit) floating point and 8 bit floating point.

Praveen Kumar Jhariya, Nitesh Dodkey

FFT, FPGA, Hardware Reuse, Butterfly

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Publication Details

Published in : Volume 2 | Issue 1 | January-Febuary - 2016
Date of Publication Print ISSN Online ISSN
2016-02-25 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
52-58 IJSRSET162114   Technoscience Academy

Cite This Article

Praveen Kumar Jhariya, Nitesh Dodkey, "Implementation of Fast Fourier Transform using Resource Reuse Technique on FPGA ", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.52-58, January-Febuary-2016.
URL : http://ijsrset.com/IJSRSET162114.php

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