A Survey on Different Multiplier Architectures

Authors(2) :-Sonam Pardhi, Nitesh Dodkey

This paper presents a comparative analysis of different multiplier architectures. The different multipliers architectures are array multiplier, a column bypass multiplier, row bypass multiplier and an array multiplier using Reversible Logic schemes. The multipliers are implemented on Spartan 2 FPGA. The architectures are compared in terms of critical path delay, power dissipation and area (resource usage in FPGA). The different multipliers are compared in terms of dynamic power consumption due to the scaling effects on leakage current. Each of these multipliers has its own trade-offs between power and delay. At last a novel multiplier is proposed, in which the number of layers is reduced to three, this will reduce the hardware resource usage and power consumption of design.

Authors and Affiliations

Sonam Pardhi
Department of Electronics and Communication Engineering, Surbhi Group of Institute, Madhya Pradesh, India
Nitesh Dodkey
Department of Electronics and Communication Engineering, Surbhi Group of Institute, Madhya Pradesh, India

Low Power, Multiplier, Switching Delay, Bypassing Techniques, Reversible Logic.

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Publication Details

Published in : Volume 2 | Issue 1 | January-February 2016
Date of Publication : 2016-02-25
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 59-64
Manuscript Number : IJSRSET162115
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Sonam Pardhi, Nitesh Dodkey, " A Survey on Different Multiplier Architectures , International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.59-64, January-February-2016.
Journal URL : http://ijsrset.com/IJSRSET162115

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