A Survey on Different Multiplier Architectures
Keywords:
Low Power, Multiplier, Switching Delay, Bypassing Techniques, Reversible Logic.Abstract
This paper presents a comparative analysis of different multiplier architectures. The different multipliers architectures are array multiplier, a column bypass multiplier, row bypass multiplier and an array multiplier using Reversible Logic schemes. The multipliers are implemented on Spartan 2 FPGA. The architectures are compared in terms of critical path delay, power dissipation and area (resource usage in FPGA). The different multipliers are compared in terms of dynamic power consumption due to the scaling effects on leakage current. Each of these multipliers has its own trade-offs between power and delay. At last a novel multiplier is proposed, in which the number of layers is reduced to three, this will reduce the hardware resource usage and power consumption of design.
References
- T. Nishitani, “Micro-programmable DSP chip,” 14th Workshop on Circuits and Systems, pp.279-280, 2001.
- V. G. Moshnyaga and K. Tamaru, “A comparative study of switching activity reduction techniques for design of low power multipliers,” IEEE International Symposium on Circuits and Systems, pp.1560-1563, 1995.
- Wu, “High performance adder cell for low power pipelined multiplier,” IEEE International Symposium on Circuits and Systems, pp.57–60, 1996.
- T. Ahn and K. Choi, “dynamic operand interchange for low power,” Electronics Letters, Vol. 33, no. 25, pp.2118- 2120,1997.
- J. Choi, J. Jeon and K. Choi, “Power minimization of functional units by partially guarded computation,” International Symposium on Low-power Electronics and Design, pp.131-136, 2000.
- J. Ohban, V. G. Moshnyaga, and K. Inoue, “Multiplier energy reduction through bypassing of partial products,” IEEE Asia-Pacific Conference on Circuits and Systems, pp.13–17, 2002.
- M. C. Wen, S. J. Wang and Y. M. Lin, “Low power parallel multiplier with column bypassing,“ IEEE International Symposium on Circuits and Systems, pp.1638- 1641, 2005.
- G. N. Sung, Y. J. Ciou and C. C. Wang, “A power-aware 2- dimensional bypassing multiplier using cell-based design flow,” IEEE International Symposium on Circuits and Systems, pp.3338-3341, 2008.
- J. T. Yan and Z. W. Chen, “Low-power multiplier design with row and column bypassing,” IEEE International SOC Conference, pp.227-230, 2009.
- Jin-Tai Yan and Zhi-Wei Chen, “low-power multiplier design with row and column bypassing”, department of computer science and information engineering, chung-hua University.
- Tushar V. More and Dr. R.V. Ksirsagar “Design of low power column bypass multiplier using FPGA” 2011 IEE
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