High Speed Area Efficient Vedic Multiplier using Barrel Shifter

Authors(2) :-Vikram Singh, Yogesh Khandagre

This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized 8-bit barrel shifter which requires only one clock cycle for n number of shifts. The propagation delay comparison was extracted from the synthesis report and static timing report as well. The design could achieve propagation delay of 8.547 using barrel shifter in base selection module and multiplier.

Authors and Affiliations

Vikram Singh
ECE Department, Trinity Institute of Technology & Research, Bhopal, India
Yogesh Khandagre
ECE Department, Trinity Institute of Technology & Research, Bhopal, India

Barrel Shifter, Base Selection Module, Propagation Delay, Power Index Determinant

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Publication Details

Published in : Volume 2 | Issue 1 | January-February 2016
Date of Publication : 2016-02-25
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 71-75
Manuscript Number : IJSRSET162125
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Vikram Singh, Yogesh Khandagre, " High Speed Area Efficient Vedic Multiplier using Barrel Shifter, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.71-75, January-February-2016.
Journal URL : http://ijsrset.com/IJSRSET162125

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