High Speed Area Efficient Vedic Multiplier using Barrel Shifter

Authors

  • Vikram Singh  ECE Department, Trinity Institute of Technology & Research, Bhopal, India
  • Yogesh Khandagre  ECE Department, Trinity Institute of Technology & Research, Bhopal, India

Keywords:

Barrel Shifter, Base Selection Module, Propagation Delay, Power Index Determinant

Abstract

This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized 8-bit barrel shifter which requires only one clock cycle for ‘n’ number of shifts. The propagation delay comparison was extracted from the synthesis report and static timing report as well. The design could achieve propagation delay of 8.547 using barrel shifter in base selection module and multiplier.

References

  1. Pavan Kumar, Saiprasad Goud A, and A Radhika had published their research with the title “FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter”, 978-1-4673-6150-7/13 IEEE.
  2. B.Madhu Latha1, B. Nageswar Rao, published their research with title “Design and Implementation of High Speed 8-Bit Vedic Multiplier on FPGA” International Journal of Advanced Research in Electrical ,Electronics and Instrumentation Engineering, Vol. 3, Issue 8, August 2014.
  3. A Murali, G Vijaya Padma , T Saritha, published their research with title “An Optimized Implementation of Vedic Multiplier Using Barrel Shifter in FPGA Technology”,  Journal of Innovative Engineering 2014, 2(2).
  4. SwetaKhatri , Ghanshyam Jangid, “FPGA Implementation of 64-bit fast multiplier using barrel shifter” Vol. 2 Issue VII, July 2014 ISSN: 2321-9653.
  5. Toni J.Billore, D.R.Rotake,  “FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders” Journal of VLSI and Signal Processing, Volume 4, Issue 3, Ver. II (May-Jun. 2014), PP 54-59 e-ISSN: 2319 – 200, p-ISSN No. : 2319 – 4197.
  6. S. S. Kerur, Prakash Narchi, Jayashree C N, Harish M Kittur and Girish V A, “Implementation of Vedic Multiplier for Digital Signal processing” International Conference on VLSI, Communication & Instrumentation (ICVCI) 2011.
  7. Vaibhav Jindal, Mr. Navaid Zafar Rizvi, Dinesh Kumar Singh “VHDL Code of Vedic Multiplierwith Minimum Delay Architecture” National Conference on Synergetic Trends in engineering and Technology (STET-2014) International Journal of Engineering and Technical Research ISSN: 2321-0869, Special Issue.
  8. Bhavin D Marul, Altaf Darvadiya “VHDL Implementation of 8-Bit Vedic Multiplier Using Barrel Shifter” International Journal for Scientific Research & Development| Vol. 2, Issue 01, 2014 | ISSN (online): 2321-0613.
  9. Gundlapalle Nandakishore, K.V.Rajendra Prasad “Fpga Implementation of 8-Bit Vedic Multiplier by Using Complex Numbers” ISSN : 2248-9622, Vol. 4, Issue 6( Version 5), June 2014, pp.265-270
  10. Ananda Kiran1 and Navdeep Prashar2 “ FPGA Implementation of High Speed Baugh-Wooley Multiplier using Decomposition Logic”
  11. L Kishore Kumar Reddy, M Venkata Subbaiah A “High Speed Vedic Multiplier Using Nikhilam Sutra with Barrel Shifte ”(An ISO 3297: 2007 Certified Organization) Vol.2, Special Issue 4, September 2014
  12. Pranali  Thakre1, Dr. Sanjay Dorle2, “Low Power 64bit Multiplier Design by Vedic Mathematics” Volume 3, Issue 4, April 2014 ISSN 2319 – 4847
  13. Sulakshna Thakur#1, Pardeep Kumar “Area-Efficient & High Speed Ripple Carry based Vedic Multiplier” SSRG International Journal of Electronics and Communication Engineering (SSRG-IJECE) – EFES April 2015
  14. Surbhi Bhardwaj1, Ashwin Singh Dodan  “Design of High Speed Multiplier using Vedic Mathematics” International Journal of Engineering Research and General Science Volume 2, Issue 4, June-July, 2014 ISSN 2091-273
  15. Swaroop A. Gandewar1, Prof. Mamta Sarde2 “Design of 8 Bit Vedic Multiplier Using VHDL” National Conference OnResearch Trends In Electronics, Computer Science & Information Technology And Doctoral Research Meet, Feb 21st & 22nd

International Journal of Scientific Research in Science, Engineering and Technology

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Published

2016-02-25

Issue

Volume 2, Issue 1, January-February-2016

Section

Research Articles

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Copyright (c) IJSRSET

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Vikram Singh, Yogesh Khandagre, " High Speed Area Efficient Vedic Multiplier using Barrel Shifter, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.71-75, January-February-2016.