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High Speed Area Efficient Vedic Multiplier using Barrel Shifter

Authors(2):

Vikram Singh, Yogesh Khandagre
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This paper describes the implementation of an 8-bit Vedic multiplier enhanced in terms of propagation delay when compared with conventional multiplier like array multiplier, Braun multiplier, modified booth multiplier and Wallace tree multiplier. In our design we have utilized 8-bit barrel shifter which requires only one clock cycle for n number of shifts. The propagation delay comparison was extracted from the synthesis report and static timing report as well. The design could achieve propagation delay of 8.547 using barrel shifter in base selection module and multiplier.

Vikram Singh, Yogesh Khandagre

Barrel Shifter, Base Selection Module, Propagation Delay, Power Index Determinant

  1. Pavan Kumar, Saiprasad Goud A, and A Radhika had published their research with the title “FPGA Implementation of high speed 8-bit Vedic multiplier using barrel shifter”, 978-1-4673-6150-7/13 IEEE.
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  5. Toni J.Billore, D.R.Rotake,  “FPGA implementation of high speed 8 bit Vedic Multiplier using Fast adders” Journal of VLSI and Signal Processing, Volume 4, Issue 3, Ver. II (May-Jun. 2014), PP 54-59 e-ISSN: 2319 – 200, p-ISSN No. : 2319 – 4197.
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Publication Details

Published in : Volume 2 | Issue 1 | January-Febuary - 2016
Date of Publication Print ISSN Online ISSN
2016-02-25 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
71-75 IJSRSET162125   Technoscience Academy

Cite This Article

Vikram Singh, Yogesh Khandagre, "High Speed Area Efficient Vedic Multiplier using Barrel Shifter", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.71-75, January-Febuary-2016.
URL : http://ijsrset.com/IJSRSET162125.php

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