Performance Optimization of Low Leakage and Low Power 8T SRAM Cell

Authors(2) :-Sandhya Patel, Somit Pandey

With CMOS technology scaling down to 65nm or below, Leakage current and leakage power and sub-threshold leakage current has been primary challenges for SRAM design and fabrication. In this paper, we introduce a low leakage and low power 8T SRAM cell. This cell is very essential for low power applications. The proposed 8T SRAM cell has been improve the dynamic current and reduces the leakage current and leakage power. To determine the performance of 8T SRAM cell under 45nm technology, we need to orCad pSpice A/D tool. This tool is very essential for transient analysis to calculate the yield accurately and efficiently. This paper presents the analysis and simulation of 8T SRAM cell with different parameters such as leakage current, leakage power and dynamic current.

Authors and Affiliations

Sandhya Patel
M. Tech. Student of Infinity Management & Engineering College, Sagar, India
Somit Pandey
Asst. Prof., Department of Electronics and Communication Engineering, Infinity Management & Engineering College, Sagar, India

SRAM, Leakage Current, Dynamic Current, Leakage Power, Word Line, Bit Line

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Publication Details

Published in : Volume 2 | Issue 1 | January-February 2016
Date of Publication : 2016-02-29
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 450-454
Manuscript Number : IJSRSET162164
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Sandhya Patel, Somit Pandey, " Performance Optimization of Low Leakage and Low Power 8T SRAM Cell, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.450-454, January-February-2016.
Journal URL : http://ijsrset.com/IJSRSET162164

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