IJSRSET calls volunteers interested to contribute towards the scientific development in the field of Science, Engineering and Technology

Home > IJSRSET162164                                                     


Performance Optimization of Low Leakage and Low Power 8T SRAM Cell

Authors(2):

Sandhya Patel, Somit Pandey
  • Abstract
  • Authors
  • Keywords
  • References
  • Details
With CMOS technology scaling down to 65nm or below, Leakage current and leakage power and sub-threshold leakage current has been primary challenges for SRAM design and fabrication. In this paper, we introduce a low leakage and low power 8T SRAM cell. This cell is very essential for low power applications. The proposed 8T SRAM cell has been improve the dynamic current and reduces the leakage current and leakage power. To determine the performance of 8T SRAM cell under 45nm technology, we need to orCad pSpice A/D tool. This tool is very essential for transient analysis to calculate the yield accurately and efficiently. This paper presents the analysis and simulation of 8T SRAM cell with different parameters such as leakage current, leakage power and dynamic current.

Sandhya Patel, Somit Pandey

SRAM, Leakage Current, Dynamic Current, Leakage Power, Word Line, Bit Line

  1. K. Bowman, et al., “Impact of die-to-die and within die parameter fluctuations on the maximum clock frequency distribution for gigascale integration,” IEEE J. Solid-State Circuits, vol. 37, no. 2, pp. 183-190, Feb. 2002.
  2. S. Borkar, et al., “Parameter variations and impact on circuits and microarchitecture,” ACWIEEE DAC, pp. 338-342, 2003.
  3. T. Karnik, T. De, and S. Borkar, “Statistical design for variation tolerance: key to continued Moore’s law,” in Proc. Int. Conf. Integrated Circuit Design and Technology, pp. 175-176, 2004.
  4. Zhang, L., Wu, C., Mao, L., & Zheng, J. , “Integrated SRAM compiler with clamping diode to reduce leakage and dynamic power in nano-CMOS process,” Micro & Nano Letters, no.2, pp.171–173, 2012.
  5. Van der Meer, P. R., van Staveren, A., & van Roermund, A. H. M., “ Ultra-low standby-currents for deep sub-micron VLSI CMOS circuits: Smart series switch,”  In Proceedings of IEEE international symposium on circuits and systems, pp. 1–4, 2004.
  6. Birla, S., Singh, R. K., & Pattanaik, M., “Static noise margin analysis of various SRAM topologies,” IACSIT International Journal of Engineering and Technology, no. 3, pp. 304–309, 2011.
  7. Birla, S., Shukla, N., Pattanaik, M., & Singh, R. K., “Device and circuit design challenges for low leakage SRAM for ultra-low power applications,” Canadian Journal on Electrical and Electronics Engineering, no. 1, pp. 11–15, 2010.
  8. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits,” in Proc. IEEE, vol. 91, no. 2pp. 305–327, 2003.
  9. Aminul Islam  and Mohd. Hassan, “Variability Analysis of 6T and 7T SRAM Cell in Sub-45nm Technology,” IIUM Engineering Journal, Vol. 12, No. 1, 2011.
  10. Naagesh. S. Bhat, “Design and Modelling of Different SRAM’s Based on CNTFET 32nm Technology,” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.1, February 2012.

Publication Details

Published in : Volume 2 | Issue 1 | January-Febuary - 2016
Date of Publication Print ISSN Online ISSN
2016-02-29 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
450-454 IJSRSET162164   Technoscience Academy

Cite This Article

Sandhya Patel, Somit Pandey, "Performance Optimization of Low Leakage and Low Power 8T SRAM Cell", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.450-454, January-Febuary-2016.
URL : http://ijsrset.com/IJSRSET162164.php