Implementation of Discrete Cosine Transform using Common Boolean Logic Adder

Authors

  • Neelam Sharma  Trinity Institute of Technology and Research, Bhopal Madhya Pradesh, India
  • Vipul Agrawal  Trinity Institute of Technology and Research, Bhopal Madhya Pradesh, India

Keywords:

Discrete Cosine Transform (DCT), Inverse discrete Cosine Transform (IDCT), VHDL

Abstract

Low-power design is one of the most important challenges to maximize battery life in portable devices and to save the energy during system operation. Discrete Cosine Transform (DCT) is widely used in image and video compression standards. In this paper, we review on a low-power DCT (Discrete Cosine Transform) architecture using varies techniques. Discrete Cosine Transform (DCT) is one of the most popular lossy techniques used today in video compression schemes. Several algorithms have been proposed to implement the DCT. Loeffler (1989) has given a new class of 1D-DCT using just 11 multiplications and 29 additions. To implement such an algorithm, one or more multipliers have to be integrated. This requires a high silicon occupation area. Arithmetic distribution is widely used for such algorithms. The coding for reconfigurable 8 point DCT has been done using VHDL under Xilinx platform.

References

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2016-02-28

Issue

Volume 2, Issue 1, January-February-2016

Section

Research Articles

License

Copyright (c) IJSRSET

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Neelam Sharma, Vipul Agrawal, " Implementation of Discrete Cosine Transform using Common Boolean Logic Adder , International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 1, pp.359-362, January-February-2016.