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Performance Analysis of Flagged BCD Adder and Pipelined BCD Adder

Authors(2):

Ullas. S. S, S .S. Ravishankar
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BCD Adder is the fundamental adder we learn in logic design and any basic electronics lab. Conventional BCD Adder what we generally know is not feasible for higher bits as they require more area and as they have more propagation delay for higher bit extension. For higher level application BCD design we require more efficient basic BCD block. So in this paper we proposed 2 types of BCD adders namely flagged BCD adder and pipelined BCD adder which will overcome the disadvantages of previous design and in this we will analysis the performance of all these BCD adders in terms of speed, power, area using Xilinx 14.5 and we used Verilog language for coding purpose.

Ullas. S. S, S .S. Ravishankar

BCD adders, Parallel Adders, Pipelining Adder, Computer Arithmetic, Power, Delay

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Publication Details

Published in : Volume 2 | Issue 2 | March-April - 2016
Date of Publication Print ISSN Online ISSN
2016-04-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
790-794 IJSRSET1622268   Technoscience Academy

Cite This Article

Ullas. S. S, S .S. Ravishankar, "Performance Analysis of Flagged BCD Adder and Pipelined BCD Adder", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.790-794, March-April-2016.
URL : http://ijsrset.com/IJSRSET1622268.php

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