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Performance Analysis of Flagged BCD Adder and Pipelined BCD Adder


Ullas. S. S, S .S. Ravishankar
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BCD Adder is the fundamental adder we learn in logic design and any basic electronics lab. Conventional BCD Adder what we generally know is not feasible for higher bits as they require more area and as they have more propagation delay for higher bit extension. For higher level application BCD design we require more efficient basic BCD block. So in this paper we proposed 2 types of BCD adders namely flagged BCD adder and pipelined BCD adder which will overcome the disadvantages of previous design and in this we will analysis the performance of all these BCD adders in terms of speed, power, area using Xilinx 14.5 and we used Verilog language for coding purpose.

Ullas. S. S, S .S. Ravishankar

BCD adders, Parallel Adders, Pipelining Adder, Computer Arithmetic, Power, Delay

  1. Tso-Bing Juang,Hsin-Hao Peng,Chao-Tsung Kuo."Area efficient BCD Adder,"19th IEEE/IFIP International Conference on VLSI Design,2011  Draft IEEE Standard for Floating-Point Arithmetic. New York: IEEE, Inc., 2004,
  2. Alp Arslan Bayrakci and Ahmet Akkas. Reduced Delay BCD Adder. IEEE, 2007. T. Lang, and A. Nannarelli, "Division Unit for Binary Integer Decimals," Prof. 20th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp. 1-7, 2009.
  3. T. Lang and A. Nannarelli, "A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture," IEEE Transactions on Computers,
  4. Vol. 56, No. 6, pp. 727-739, June 2007.
  5. R. K. James, T. K. Shahana, K. P. Jacob, and S. Sasi, "Decimal multiplication using compact BCD ultiplier," Proc. International Conference on Electronic Design (ICED), pp. 1-6, 2008
  6. P. M. Kogge and H. S. Stone. A Parallel Algorithm for The Efficient Solution of a General Class of Recurrence Equations.IEEE Trans. on Computers, C-22(8), Aug. 1973.
  7. M. M. Mano. Digital Design, pages 129–131. Prentice Hall, third edition, 2002.
  8. M. S. Schmookler and A.W.Weinberger. High Speed Decimal Addition. IEEE Transactions on Computers, C-20:862– 867, Aug.1971.
  9. B. Shirazi, D. Y. Y. Young, and C. N. Zhang. RBCD: Redundant Binary Coded Decimal Adder. In IEEE Proceedings, Part E, No. 2, volume 136, pages 156–160, March 1989.
  10. J. D. Thompson, N. Karra, and M. J. SchulteB. A 64-Bit Decimal Floating-Point Adder. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pages 297– 298, February 2004.
  11. +B. Prashanthi kumari, G. N. V. Ratna Kishor, “New Approach for Implementing BCD Adder Using Flagged Logic” ternational Journal of Engineering Research & Technology IJERT) Vol. 2 Issue 12, December - 2013

Publication Details

Published in : Volume 2 | Issue 2 | March-April - 2016
Date of Publication Print ISSN Online ISSN
2016-04-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
790-794 IJSRSET1622268   Technoscience Academy

Cite This Article

Ullas. S. S, S .S. Ravishankar, "Performance Analysis of Flagged BCD Adder and Pipelined BCD Adder", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.790-794, March-April-2016.
URL : http://ijsrset.com/IJSRSET1622268.php




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