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Performance Analyzing of CMOS Gates by Sub Clocking Method Using Cadence Tools


N. Prabhu, Prof. T. Ravichandran, S. Vigneshwaran
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Reducing the power consumed by the device is the emerging trend. The aim of this project is to reduce the leakage current of the circuit by using the Sub Clocking technology. It is the process of switching the circuit by means of partially ON to reduce the power consumption. In this paper there are two modes of operation are implemented.1. Half mode operation, 2. Full mode operation. This mode of operation are implemented in the two designing method. Design-1: pMOS and nMOS are connected at the header side of the standard CMOS circuit.Design-2: pMOS and nMOS are connected at the header side of the standard CMOS circuit. pMOS and nMOS transistor at the header and footer side are refer to be as a Sub Clock control unit. Any one of the transistor is ON for a half mode operation and both the transistor are turn ON for full mode of operation. This will do by using the control signal to the unit.

N. Prabhu, Prof. T. Ravichandran, S. Vigneshwaran

CMOS, Sub Clocking Method, Cadence Tools, HOM, SCC, VDD, DML, UMC, GND

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Publication Details

Published in : Volume 2 | Issue 2 | March-April - 2016
Date of Publication Print ISSN Online ISSN
2016-04-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
1060-1064 IJSRSET1622364   Technoscience Academy

Cite This Article

N. Prabhu, Prof. T. Ravichandran, S. Vigneshwaran, "Performance Analyzing of CMOS Gates by Sub Clocking Method Using Cadence Tools", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.1060-1064, March-April-2016.
URL : http://ijsrset.com/IJSRSET1622364.php




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