Reducing the power consumed by the device is the emerging trend. The aim of this project is to reduce the leakage current of the circuit by using the Sub Clocking technology. It is the process of switching the circuit by means of partially ON to reduce the power consumption. In this paper there are two modes of operation are implemented.1. Half mode operation, 2. Full mode operation. This mode of operation are implemented in the two designing method. Design-1: pMOS and nMOS are connected at the header side of the standard CMOS circuit.Design-2: pMOS and nMOS are connected at the header side of the standard CMOS circuit. pMOS and nMOS transistor at the header and footer side are refer to be as a Sub Clock control unit. Any one of the transistor is ON for a half mode operation and both the transistor are turn ON for full mode of operation. This will do by using the control signal to the unit.
N. Prabhu, Prof. T. Ravichandran, S. Vigneshwaran
CMOS, Sub Clocking Method, Cadence Tools, HOM, SCC, VDD, DML, UMC, GND
- Asaf Kaizerman,sagiFisherandAlexander Fish "SubThreshold Dual Mode Logic" IEEE Trans. Very Large Scale Integration(VLSI) System, vol. 29, no. 5, pp. 979–983, may- 2013.
- Jatin N.Mistry "Active Mode Subclock power gating" IEEE Trans. VLSI SYSTEMS, journal accepted,august 20,2013.
- N. Mehta and B. Amrutur, "Dynamic supply and threshold voltage scaling for CMOS digital circuits using in-situ power monitor," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 20, no. 5, pp. 892–901, May 2012.
- J. Seomun, I. Shin, and Y. Shin, "Synthesis of active-mode power gating circuits," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 31, no. 3, pp. 391–403, Mar. 2012.
- M. Alioto, "Ultralow power VLSI circuit design demystified and explained: A tutorial," IEEE Trans. Circuits Syst. I, vol. 59, no. 1, pp. 3–29, Jan. 2012.
- X. Liu, Y. Zheng, M. W. Phyu, F. N. Endru, V. Navaneethan, and B. Zhao, "An ultra-low power ECG acquisition and monitoring ASIC system for WBAN applications," IEEE J. Emerging Sel. Topics Circuits Syst., vol. 2, no. 1, pp. 60–70, Mar. 2012.
- D. Markovic, C. C. Wang, L. P. Alarcon, and J. M. Rabaey, "Ultralow power design in near-threshold region," Proc. IEEE, vol. 98, no. 2, pp. 237–252, Feb. 2010.
- Y. Pu, J. P. de Gyvez, H. Corporaal, and Y. Ha, "An ultralowenergy/ frame multi-standard JPEG co-processor in 65 nm CMOS with sub/near-threshold power supply," in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2009, pp. 146–147.
|Published in :
||Volume 2 | Issue 2 | March-April - 2016
|Date of Publication
Cite This Article
N. Prabhu, Prof. T. Ravichandran, S. Vigneshwaran, "Performance Analyzing of CMOS Gates by Sub Clocking Method Using Cadence Tools", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.1060-1064, March-April-2016.
URL : http://ijsrset.com/IJSRSET1622364.php