Large bus width increases the problem of interconnections in the modern system on chip (SOC) design. Interconnection increases the delay, area and energy consumption in CMOS digital circuits. For design circuitry in VLSI, multiple-valued logic (MVL) plays a very vital role. MVL is an apparent extension of binary logic where any proposition can have more than two values. Dynamic power requirement can be reduced by using the concept of level transition in multiple-valued logic. MVL is also helps to reduce the number of interconnections. It provides the key benefit of a higher density per integrated circuit area compared to traditional binary logic. In this paper, we are presenting an application of these circuits with response to Galois field operations and also a quaternary converter circuits using Down Literal Circuit (DLC). Arithmetic operations such as addition and multiplication are the two basic operations in Galois field. Tanner has created a software platform that is cost-effective and easy to use.
T. R. Harinkhede, Pooja R. Thakare, Puja R. Tonde, Snehal B. Patil, Divya R. Savale, Koyal T. Karare, Manisha P. Dongre
Down Literal Circuit, Galois Field, Multiple-valued logic, Quaternary logic, Standard CMOS Technology, Very Large Scale Integrated Circuit.
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||Volume 2 | Issue 2 | March-April - 2016
|Date of Publication
Cite This Article
T. R. Harinkhede, Pooja R. Thakare, Puja R. Tonde, Snehal B. Patil, Divya R. Savale, Koyal T. Karare, Manisha P. Dongre, "Multi-Valued Logic Concept for Galois Field Arithmetic Logic Unit", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.350-355, March-April-2016.
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