Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images

Authors

  • N. Megala  Department of ECE, SNS College of Technology, Coimbatore, Tamil Nadu, India
  • N. Rajeswaran  Department of ECE, SNS College of Technology, Coimbatore, Tamil Nadu, India

Keywords:

Algorithmic noise tolerant (ANT), fixed-width multi¬plier, reduced-precision replica (RPR), voltage overscaling (VOS) and error correction block (EC)

Abstract

In area efficient low error compensation multiplier design is using fixed width RPR(Reduced Precision Redundancy). We propose a new method called fixed width RPR for DSP applications. This fixed width multiplier is placed in ANT architecture to meet high speed, low power consumption and area efficiency. The fixed RPR is designed with compensation circuit for minimizing the occurrence of error. The nxn bit is used as a input. The partial product term is used in RPR block for input correction vector and trivial input modification vector to worse the truncation errors. To achieve more precise error compensation. Variable correction value is used the truncation error can be compensation circuit is minimized. This circuit can be use in applications of image processing. By using this multiplier we merge the two images into compressed single image.

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2017-12-31

Issue

Volume 2, Issue 2, March-April-2016

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Research Articles

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How to Cite

[1]
N. Megala, N. Rajeswaran, " Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.261-264, March-April-2016.