IJSRSET calls volunteers interested to contribute towards the scientific development in the field of Science, Engineering and Technology

Home > IJSRSET162241                                                     

Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images


N. Megala, N. Rajeswaran
  • Abstract
  • Authors
  • Keywords
  • References
  • Details
In area efficient low error compensation multiplier design is using fixed width RPR(Reduced Precision Redundancy). We propose a new method called fixed width RPR for DSP applications. This fixed width multiplier is placed in ANT architecture to meet high speed, low power consumption and area efficiency. The fixed RPR is designed with compensation circuit for minimizing the occurrence of error. The nxn bit is used as a input. The partial product term is used in RPR block for input correction vector and trivial input modification vector to worse the truncation errors. To achieve more precise error compensation. Variable correction value is used the truncation error can be compensation circuit is minimized. This circuit can be use in applications of image processing. By using this multiplier we merge the two images into compressed single image.

N. Megala, N. Rajeswaran

Algorithmic noise tolerant (ANT), fixed-width multiĀ¬plier, reduced-precision replica (RPR), voltage overscaling (VOS) and error correction block (EC)

  1. B. Shim, S. Sridhara, and N. R. Shanbhag, “Reliable low-power digital signal processing via reduced precision redundancy,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 5, pp. 497–510,May 2004.
  2. B. Shim and N. R. Shanbhag, “Energy-efficient soft-error tolerant digital signal processing,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,vol. 14, no. 4, pp. 336–348, Apr. 2006.
  3. R. Hedge and N. R. Shanbhag, “Energy-efficient signal processing via algorithmic noise-tolerance,” in Proc. IEEE Int. Symp. Low Power Electron. Des., Aug. 1999, pp. 30–35.
  4. V. Gupta, D. Mohapatra, A. Raghunathan, and K. Roy, “Low-power digital signal processing using approximate adders,” IEEE Trans. Comput. Added Des. Integr. Circuits Syst., vol. 32, no. 1, pp. 124–137, Jan. 2013.
  5. Y. Liu, T. Zhang, and K. K. Parhi, “Computation error analysis in digital signal processing systems with overscaled supply voltage,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 4, pp. 517–526 Apr. 2010.
  6. J. N. Chen, J. H. Hu, and S. Y. Li, “Low power digital signal processing scheme via stochastic logic protection,” in Proc. IEEE Int. Symp. Circuits Syst., May 2012, pp. 3077–3080.
  7. J. N. Chen and J. H. Hu, “Energy-efficient digital signal processing via voltage-overscaling-based residue number system,” IEEE Trans.Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 7, pp. 1322–1332,Jul. 2013.
  8. P. N. Whatmough, S. Das, D. M. Bull, and I. Darwazeh, “Circuit-level timing error tolerance for low-power DSP filters and transforms,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 6, pp. 12–18, Feb. 2012.
  9. G. Karakonstantis, D. Mohapatra, and K. Roy, “Logic and memory design based on unequal error protection for voltage-scalable, robust and adaptive DSP systems,” J. Signal Process. Syst., vol. 68, no. 3, pp. 415–431, 2012.
  10. Y. Pu, J. P. de Gyvez, H. Corporaal, and Y. Ha, “An ultra low energy/frame multi-standard JPEG co-processor in 65-nm CMOS with sub/near threshold power supply,” IEEE J. Solid State Circuits, vol. 45, no. 3, pp. 668–680, Mar. 2010.
  11. H. Fuketa, K. Hirairi, T. Yasufuku, M. Takamiya, M. Nomura,H. Shinohara, et al., “12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics,” in Proc. ISLPED, Fukuoka, Japan, Aug. 2011, pp. 163–168.
  12. Y. C. Lim, “Single-precision multiplier with reduced circuit complexity for signal processing applications,” IEEE Trans. Comput., vol. 41, no. 10,pp. 1333–1336, Oct. 1992.
  13. M. J. Schulte and E. E. Swartzlander, “Truncated multiplication with correction constant,” in Proc. Workshop VLSI Signal Process., vol. 6. 1993, pp. 388–396.
  14. S. S. Kidambi, F. El-Guibaly, and A. Antoniou, “Area-efficient multipliers for digital signal processing applications,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 43, no. 2, pp. 90–95, Feb. 1996.
  15. J. M. Jou, S. R. Kuang, and R. D. Chen, “Design of low-error fixed-width multipliers for DSP applications,” IEEE Trans. Circuits Syst., vol. 46, no. 6, pp. 836–842, Jun. 1999.

Publication Details

Published in : Volume 2 | Issue 2 | March-April - 2016
Date of Publication Print ISSN Online ISSN
2016-04-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
261-264 IJSRSET162241   Technoscience Academy

Cite This Article

N. Megala, N. Rajeswaran, "Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.261-264, March-April-2016.
URL : http://ijsrset.com/IJSRSET162241.php