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Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images

Authors(2):

N. Megala, N. Rajeswaran
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In area efficient low error compensation multiplier design is using fixed width RPR(Reduced Precision Redundancy). We propose a new method called fixed width RPR for DSP applications. This fixed width multiplier is placed in ANT architecture to meet high speed, low power consumption and area efficiency. The fixed RPR is designed with compensation circuit for minimizing the occurrence of error. The nxn bit is used as a input. The partial product term is used in RPR block for input correction vector and trivial input modification vector to worse the truncation errors. To achieve more precise error compensation. Variable correction value is used the truncation error can be compensation circuit is minimized. This circuit can be use in applications of image processing. By using this multiplier we merge the two images into compressed single image.

N. Megala, N. Rajeswaran

Algorithmic noise tolerant (ANT), fixed-width multiĀ¬plier, reduced-precision replica (RPR), voltage overscaling (VOS) and error correction block (EC)

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Publication Details

Published in : Volume 2 | Issue 2 | March-April - 2016
Date of Publication Print ISSN Online ISSN
2016-04-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
261-264 IJSRSET162241   Technoscience Academy

Cite This Article

N. Megala, N. Rajeswaran, "Low Error Compensation Fixed width RPR Multiplier Design Using in Merging of Images", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.261-264, March-April-2016.
URL : http://ijsrset.com/IJSRSET162241.php

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