An Efficient, Low Power 256X8 T-SRAM Architecture

Authors

  • S. MD. Imran Ali  Department of Electronics and Communication Engineering, Brindavan Institute of Tech & Science, Kurnool, Andhra Pradesh, India
  • B. V. Ramana  Department of Electronics and Communication Engineering, Brindavan Institute of Tech & Science, Kurnool, Andhra Pradesh, India
  • J. Harishwariah  Department of Electronics and Communication Engineering, Brindavan Institute of Tech & Science, Kurnool, Andhra Pradesh, India
  • T. Shiva Shankara Vara Prasad  Department of Electronics and Communication Engineering, Brindavan Institute of Tech & Science, Kurnool, Andhra Pradesh, India

Keywords:

CAM ,LUT, SRAM, TCAM,TLB

Abstract

High-speed lookup operations are performed by Ternary Content addressable memories. But TCAMs are limited due to low storage density, relatively access time, low scalability, complex circuitry, and are very expensive in comparison with static random access memories (SRAMs).The benefits of SRAM are availed by configuring an additional logic to enable SRAM to behave like a TCAM. T-SRAM is proposed novel memory architecture that emulates the TCAM functionality with SRAM. T-SRAM logically partitions the classical TCAM table along columns and rows into hybrid TCAM sub tables, which are then processed to map on their corresponding memory blocks .A 256x8 T-SRAM is implemented that consumes 0.024 W.

References

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2017-12-31

Issue

Volume 2, Issue 2, March-April-2016

Section

Research Articles

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
S. MD. Imran Ali, B. V. Ramana, J. Harishwariah, T. Shiva Shankara Vara Prasad, " An Efficient, Low Power 256X8 T-SRAM Architecture, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.301-305, March-April-2016.