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An Efficient, Low Power 256X8 T-SRAM Architecture

Authors(4):

S. MD. Imran Ali, B. V. Ramana, J. Harishwariah, T. Shiva Shankara Vara Prasad
  • Abstract
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High-speed lookup operations are performed by Ternary Content addressable memories. But TCAMs are limited due to low storage density, relatively access time, low scalability, complex circuitry, and are very expensive in comparison with static random access memories (SRAMs).The benefits of SRAM are availed by configuring an additional logic to enable SRAM to behave like a TCAM. T-SRAM is proposed novel memory architecture that emulates the TCAM functionality with SRAM. T-SRAM logically partitions the classical TCAM table along columns and rows into hybrid TCAM sub tables, which are then processed to map on their corresponding memory blocks .A 256x8 T-SRAM is implemented that consumes 0.024 W.

S. MD. Imran Ali, B. V. Ramana, J. Harishwariah, T. Shiva Shankara Vara Prasad

CAM ,LUT, SRAM, TCAM,TLB

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Publication Details

Published in : Volume 2 | Issue 2 | March-April - 2016
Date of Publication Print ISSN Online ISSN
2016-03-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
301-305 IJSRSET162290   Technoscience Academy

Cite This Article

S. MD. Imran Ali, B. V. Ramana, J. Harishwariah, T. Shiva Shankara Vara Prasad, "An Efficient, Low Power 256X8 T-SRAM Architecture", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 2, pp.301-305, March-April-2016.
URL : http://ijsrset.com/IJSRSET162290.php

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