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Study and Review on VLSI Design Methodologies and Limitations using CMOS Adder Circuits


Niranjan Kumar, Vipul Aggarwal
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In this review paper different design techniques of multi bit adder are deliberate using linear parameters logic gates. The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power dissipation, power delay product (PDP), average power dissipation time delay and size of the full adder circuit. Adder circuits basically implemented using basic logic gates namely XOR and AND gates. Half Adders or Full adders may be realized in various ways depending on the various process technologies and design methodologies deployed for making these digital integrated circuits design. The Full adder, 14T, pseudo-nMOS, MULTIPLEXER-BASED FULL ADDER , 8T, Inverter-based full-adder with pass transistors, Conventional CMOS (C-CMOS), 20T,10Twith 4T-XNOR, 6T, 16T, 9T, Double gate MOSFET and hybrid 1-bit full adder full adders etc

Niranjan Kumar, Vipul Aggarwal

CMOS, Adders, VLSI Design, CAD, process technology, delay analysis

  1. Randal E. Bryant, Kwang-TingCheng , Andrew B Kahang, Kurt Kreutzer, Wojciech Maly,Richard Newton, Lawerance Pileggi, Jan M Rabaey, Alberto Saniovanni- Vincentelli, “Limitations and Challenges of CAD technology for CMOS VLSI”
  2. S. Roy and C. T. Bhunia, “On Synthesis of Combinational Logic Circuits,” International Journal of Computer Applications, vol. 127,no 1, pp. 21-26, 2015.”
  3. A.H. Farrahi, D.J. Hathaway, M.Wang and M.Sarrafzadeh, “Quality OF EDA CAD Tools: Definitions, Metrices and Directions”
  4. Anantha Chandrakasan, Isabel Yang, Carlin Veiri, Dimitri Antoniadis, “Design Considerations and tools for Low voltage Digital system Design”
  5. Mike Spreitzer “Comparing Structurally different views of a VLSI Design”
  6. Catherine H. Gebotys, Mohamed I. Elmasry, “VLSI Design Synthesis and Testibility”
  7. T.S. Cheung, K.Asada, K.L. Yip, H. Wong, Y.C. Cheng, “Low Power CMOS Design Methodologies with reduced voltage swing ”
  8. K.A. Sumithra Devi, “Algorithms for CAD tools VLSI design”
  9. Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic, “Digital Integrated Circuits” , A Design perspective Second edition
  10. Dr. Nicos Bilalis, “Computer Aided Design CAD”, January 2000 edition
  11. Course: “Trends in VLSI Design: Methodologies and CAD tools”. Presenter Raj Singh. IC Design group,CEERI,Pilani-333031
  12. P.van der Wolf. “CAD Frameworks: Principle and Architecture” Kluwer Academic Publishers,236pp
  13. K.Chaudhary, A.Onawaza, and E.S. Kuh. “Algorithms for Performance Enhancement and Crosstalk Reduction”. In International conference on Computer Aided Design, pages 697-702,1993.
  14. C.Chen and M.Sarrafzadeh. “Provably Good Algorithm for low power consumption and supply voltages” ”. In International conference on Computer Aided Design, pages 76-79,1999.

Publication Details

Published in : Volume 2 | Issue 3 | May-June - 2016
Date of Publication Print ISSN Online ISSN
2016-06-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
449-453 IJSRSET1623134   Technoscience Academy

Cite This Article

Niranjan Kumar, Vipul Aggarwal, "Study and Review on VLSI Design Methodologies and Limitations using CMOS Adder Circuits", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 3, pp.449-453, May-June-2016.
URL : http://ijsrset.com/IJSRSET1623134.php