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Study and Review on VLSI Design Methodologies and Limitations using CMOS Adder Circuits

Authors(2):

Niranjan Kumar, Vipul Aggarwal
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In this review paper different design techniques of multi bit adder are deliberate using linear parameters logic gates. The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power dissipation, power delay product (PDP), average power dissipation time delay and size of the full adder circuit. Adder circuits basically implemented using basic logic gates namely XOR and AND gates. Half Adders or Full adders may be realized in various ways depending on the various process technologies and design methodologies deployed for making these digital integrated circuits design. The Full adder, 14T, pseudo-nMOS, MULTIPLEXER-BASED FULL ADDER , 8T, Inverter-based full-adder with pass transistors, Conventional CMOS (C-CMOS), 20T,10Twith 4T-XNOR, 6T, 16T, 9T, Double gate MOSFET and hybrid 1-bit full adder full adders etc

Niranjan Kumar, Vipul Aggarwal

CMOS, Adders, VLSI Design, CAD, process technology, delay analysis

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Publication Details

Published in : Volume 2 | Issue 3 | May-June - 2016
Date of Publication Print ISSN Online ISSN
2016-06-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
449-453 IJSRSET1623134   Technoscience Academy

Cite This Article

Niranjan Kumar, Vipul Aggarwal, "Study and Review on VLSI Design Methodologies and Limitations using CMOS Adder Circuits", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 3, pp.449-453, May-June-2016.
URL : http://ijsrset.com/IJSRSET1623134.php

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