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AMBA-APB RTL Implementation using Efficient Power and Constructs through Verilog

Authors(3):

Niraj Kumar Mishra, Dr. R. P. Singh, Dr. Jaikarn Singh
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The challenge in engineering VLSI based IC design to find an optimum solution for chip which will satisfy the needs of Power, area and efficiency. The aim of this paper is to design and AMBA-APB RTL which is highly efficient in power and size issues. The reusability of design and easy configurability are the focus area of this paper through which design will be implemented. The Design specification is based on ARM based AMBA_APB specification version V2.0. For the simulation task, ModelSim Version 10.3 has been used. For the synthesisation purpose, design utilization summary and power details Xilinx-ISE design software has been used. Power report is introduced for developing better and clear understanding of the power utilization and distribution in any system. The power report gives the power consumption summary.The total clocks power consumption in chip is of 0.38mW, total hierarchy power consumption of 0.52 mW and total on chip logical power consumption of 0.111 W have been extracted from Xilinx XPower analyser tool when APB Bridge is designed under the proposed design approach.

Niraj Kumar Mishra, Dr. R. P. Singh, Dr. Jaikarn Singh

RTL Constructs, Xilinx ISE 14.1, Efficient Power, Modelsim, SoC

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Publication Details

Published in : Volume 2 | Issue 3 | May-June - 2016
Date of Publication Print ISSN Online ISSN
2016-06-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
469-472 IJSRSET1623145   Technoscience Academy

Cite This Article

Niraj Kumar Mishra, Dr. R. P. Singh, Dr. Jaikarn Singh, "AMBA-APB RTL Implementation using Efficient Power and Constructs through Verilog", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 3, pp.469-472, May-June-2016.
URL : http://ijsrset.com/IJSRSET1623145.php

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