Single Electron Transistor Made Nano IC Adder for High Speed Computing

Authors(6) :-Sanjay Bhadra, Shilpa Saha, Abhradeep Ghosh, Susamman Biswas, Mouktik Bhattacharya, Shantanu Bhadra

Single electron transistor (SET) is a key element of present device research which can offer high operating speed with low power consumption. Downscaling of minimum feature size of CMOS transistor has been the basis for advancement in ultra large integration for many years. But by no means it has turned to be a never ending process. The present work demonstrates a hypothetical approach to design a single electron device based commercially viable logic circuit to be embedded in next generation IC's.

Authors and Affiliations

Sanjay Bhadra
EE Department, UEM-Kolkata, India
Shilpa Saha
CSE Department, UEM-Kolkata, India
Abhradeep Ghosh
ECE Department, UEM-Kolkata, India
Susamman Biswas
CSE Department, UEM-Kolkata, India
Mouktik Bhattacharya
EEE Department, UEM-Kolkata, India
Shantanu Bhadra
CSE Department, RAMT-Kolkata, India

SET, SED, Adder, ,Coulomb Island,Nano IC

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Publication Details

Published in : Volume 2 | Issue 3 | May-June 2016
Date of Publication : 2016-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 559-561
Manuscript Number : IJSRSET1623155
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Sanjay Bhadra, Shilpa Saha, Abhradeep Ghosh, Susamman Biswas, Mouktik Bhattacharya, Shantanu Bhadra, " Single Electron Transistor Made Nano IC Adder for High Speed Computing, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 3, pp.559-561, May-June-2016.
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