The aim of this paper is to give briefing of the concept of network-on-chip (NoC). NoC is an approach to design the communication subsystem between IP cores in a System on Chip (SoC). NoCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. This NoC brings an effective improvement over conventional busses and cross bar switches. The power requirement of the SoC is high where as it can be reduced by the NoC architecture. NoC is an developing paper in the field of VLSI. Since the use of emerging NoC architecture in VLSI it reduces the size of the architecture due to the reduced amount of buses and transmission lines. ." In a NoC system, modules such as processor cores, memories and specialized IP blocks exchange data using a network as a "public transportation" sub-system for the information traffic. The wires in the links of the NoC are shared by many signals
Anita N Pachange, Dr. S S Kerur
Network-on-Chip (NoC), synchronous and asynchronous clock, processor cores, memories and specialized IP blocks.
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|Published in :
||Volume 2 | Issue 3 | May-June - 2016
|Date of Publication
Cite This Article
Anita N Pachange, Dr. S S Kerur, "Design and Implementation of Cross Bar NoC Architecture", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 3, pp.142-146, May-June-2016.
URL : http://ijsrset.com/IJSRSET162326.php