IJSRSET calls volunteers interested to contribute towards the scientific development in the field of Science, Engineering and Technology

Home > IJSRSET162494                                                     


Constant Delay Logic Based Timing Analysis of Adder Circuits Using C5 Process Technology

Authors(2):

Niranjan Kumar, Sourabh Sharma
  • Abstract
  • Authors
  • Keywords
  • References
  • Details
A full custom logic design for adders and their timing analysis followed by FFT plots is proposed in this paper targeting high speed applications using MOSIS C5 process for CMOS. The characteristic of this logic style regardless of the logic type makes it suitable for implementing complicated arithmetic and logic circuits preferably adders and multipliers. A carry-look ahead adder (CLA) or fast adder is a type of adder used in digital logic and is presented for design and analysis. A carry-look ahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits. The carry-look ahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits. Carry Propagator and Carry Generator FFT results are compared in terms of their amplitude, phase and group delays. Several design considerations including timing window width adjustment and output distribution namely sum are discussed. Sum outputs are tabulated for multibit adders namely 4 bits and 16 bits. Their timing analysis is done using suitable SPICE code and C5 process technology.

Niranjan Kumar, Sourabh Sharma

CMOS, Adders, VLSI Design, CAD, process technology, delay analysis

  1. Chuang, Pierce, David Li, and Manoj Sachdev. "Constant delay logic style." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21.3 (2013): 554-565.Catherine H. Gebotys, Mohamed  Elmasry,  “VLSI Design Synthesis and Testability”
  2. Kanoriya, Lily, Aparna Gupta, and Soni Changlani. "Layout Designing and Transient Analysis of Carry Lookahead Adder Using 300nm Technology-A." (2016).
  3. Kumar, Raushan, Sahadev Roy, and C. T. Bhunia. "Study of Threshold Gate And CMOS Logic Style Based Full Adder Circuits." Proc. IEEE, 3rd Int. Conference on Electronics and Communication Systems (ICECS), IEEE. 2016.
  4. Babu, Hima, P. Maria Glenny, and Anto Yohan. "Comparison of Power and Area: 2 Bit Hybrid Fulladder Design With 2 Bit Full Adder Using CMOS Technology." Imperial Journal of Interdisciplinary Research 2.4 (2016).
  5. Senthilkumaran, K., and K. R. Kashwan. "Adiabatic constant delay logic style." Innovations in Information, Embedded and Communication Systems (ICIIECS), 2015 International Conference on. IEEE, 2015.
  6. Bhattacharyya, Partha, et al. "Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit." IEEE Transactions on very large scale integration (VLSI) systems 23.10 (2015): 2001-2008.
  7. Anku Bala “Layout and Design Analysis of Carry Look Ahead Adder Using 90nm Technology”, Int.Journal Of Electrical & Electronics Engg. Volume 2, .issue1, 2015.
  8. Amuthavalli G. and Gunasundari R, “Analysis Of 16-Bit Carry Look Ahead Adder – A Subthreshold Leakage PowerPerspective”, ARPN Journal of Engineering and Applied Sciences Volume-10, NO. 6, April 2015.
  9. Reethika Rao, Dr. K. Ragini, “Comparative Analysis Of 32 Bit Carry Look Ahead Adder using Constant Delay Logic”, International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 10, October 2014.
  10. Reethika Rao, Dr. K. Ragini, “Comparative Analysis Of 32 Bit Carry Look Ahead Adder using Constant Delay Logic”,International Journal of Science, Engineering and Technology Research (IJSETR), Volume 3, Issue 10, October 2014.
  11. Jagannath Samanta, Mousam Halder, Bishnu Prasad De, “Performance Analysis of High Speed Low Power Carry LookAhead Adder Using Different Logic Styles”, International Journal of Soft Computing and Engineering (IJSCE), Volume-2,Issue-6, Jan- 2013.
  12. Kathiresan, Dr. M.Thangavel, K.Rathinakumar, S.Maragadharaj, “Analysis Of Different Bit Carry Look Ahead AdderUsing Verilog Code”, International Journal of Electronics and Communication Engineering & Technology(IJECET), Volume4, Issue 4, July-August, 2013.
  13. Jatinder Kumar, Parveen Kaur, “Comparative Performance Analysis of Different CMOS Adders Using 90nm and 180nm Technology”, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET) Volume 2Issue 8, August 2013.
  14. Computer aids for VLIS http://www. rulabinsky.com/steve

Publication Details

Published in : Volume 2 | Issue 4 | July-August - 2016
Date of Publication Print ISSN Online ISSN
2016-08-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
356-363 IJSRSET162494   Technoscience Academy

Cite This Article

Niranjan Kumar, Sourabh Sharma, "Constant Delay Logic Based Timing Analysis of Adder Circuits Using C5 Process Technology", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 4, pp.356-363, July-August-2016.
URL : http://ijsrset.com/IJSRSET162494.php