A full custom logic design for adders and their timing analysis followed by FFT plots is proposed in this paper targeting high speed applications using MOSIS C5 process for CMOS. The characteristic of this logic style regardless of the logic type makes it suitable for implementing complicated arithmetic and logic circuits preferably adders and multipliers. A carry-look ahead adder (CLA) or fast adder is a type of adder used in digital logic and is presented for design and analysis. A carry-look ahead adder improves speed by reducing the amount of time required to determine carry bits. It can be contrasted with the simpler, but usually slower, ripple carry adder for which the carry bit is calculated alongside the sum bit, and each bit must wait until the previous carry has been calculated to begin calculating its own result and carry bits. The carry-look ahead adder calculates one or more carry bits before the sum, which reduces the wait time to calculate the result of the larger value bits. Carry Propagator and Carry Generator FFT results are compared in terms of their amplitude, phase and group delays. Several design considerations including timing window width adjustment and output distribution namely sum are discussed. Sum outputs are tabulated for multibit adders namely 4 bits and 16 bits. Their timing analysis is done using suitable SPICE code and C5 process technology.
Niranjan Kumar, Sourabh Sharma
CMOS, Adders, VLSI Design, CAD, process technology, delay analysis
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||Volume 2 | Issue 4 | July-August - 2016
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Cite This Article
Niranjan Kumar, Sourabh Sharma, "Constant Delay Logic Based Timing Analysis of Adder Circuits Using C5 Process Technology", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 4, pp.356-363, July-August-2016.
URL : http://ijsrset.com/IJSRSET162494.php