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Design of 16 bit Arithmetic and Logical Unit Using Vivado 14.7 and Implementation on Basys 3 FPGA Board


Prachi Sharma, G. Rama Laxmi, Arun Kumar Mishra
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This paper primarily deals with the construction of arithmetic Logic Unit (ALU) using Hardware Description Language (HDL) using Xilinx Vivado 14.7 and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. ALU of digital computers is an aspect of logic design with the objective of developing appropriate algorithms in order to achieve an efficient utilization of the available hardware. The hardware can only perform a relatively simple and primitive set of Boolean & arithmetic operations and are based on a hierarchy of operations that are built by using algorithms employing the hardware. Speed, power and utilization of ALU are the measures of the efficiency of an algorithm. In this paper, we have simulated and synthesized the various parameters of ALUs by using VHDL on Xilinx Vivado 14.7 and Basys 3 Artix 7 FPGA board.

Prachi Sharma, G. Rama Laxmi, Arun Kumar Mishra

FPGA, ALU, XILINX Vivado 14.7, Basys 3 Artix 7 FPGA Board

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Publication Details

Published in : Volume 2 | Issue 5 | September-October - 2016
Date of Publication Print ISSN Online ISSN
2016-10-30 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
243-249 IJSRSET162510   Technoscience Academy

Cite This Article

Prachi Sharma, G. Rama Laxmi, Arun Kumar Mishra, "Design of 16 bit Arithmetic and Logical Unit Using Vivado 14.7 and Implementation on Basys 3 FPGA Board", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 5, pp.243-249, September-October-2016.
URL : http://ijsrset.com/IJSRSET162510.php