Low-Power and Area Efficient Dual Dynamic Node Pulsed Hybrid Flip-Flop

Authors

  • P. Arun Kumar  Department of Electrical and Communication Engineering, SNS College of Technology, Tamilnadu, India
  • C. Yamunarani  Department of Electrical and Communication Engineering, SNS College of Technology, Tamilnadu, India

Keywords:

Elliptic curve cryptography (ECC), Montgomery multiplication, residue arithmetic, residue number system (RNS).

Abstract

Elliptic curve point multiplication (ECPM) is one of the most critical operations in elliptic curve cryptography. In this brief, a new hardware architecture for ECPM over GF( p) is presented, based on the residue number system (RNS). The proposed architecture encompasses RNS bases with various word-lengths in order to efficiently implement RNS Montgomery multiplication. Two architectures with four and six pipeline stages are presented, targeted on area-efficient and fast RNS Montgomery multiplication designs, respectively. The fast version of the proposed ECPM architecture achieves higher speeds and the area- efficient version achieves better area–delay tradeoffs compared to state- of-the-art implementations.

References

  1. N. Koblitz, "Elliptic curve cryptosystems," Math. Comp., vol. 48, no. 177, pp. 203–209, 1987.
  2. V. S. Miller, "Use of elliptic curves in cryptography," in Proc. Adv. Cryptology LNCS, 1986, pp. 47–426.
  3. I. Blake, G. Seroussi, and N. Smart, Elliptic Curves in Cryptography. Cambridge, U.K.: Cambridge Univ. Press, 2002.
  4. D. M. Schinianakis, A. P. Fournaris, H. E. Michail, A. P. Kakarountas, and T. Stouraitis, "An RNS implementation of an F p elliptic curve point multiplier," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 6, pp 1202–1213, Jun. 2009.
  5. C. J. McIvor, M. McLoone, and J. V. McCanny, "Hardware elliptic curve cryptographic processor over GF(P) ," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 9, pp. 1946–1957, Sep. 2006.
  6. G. Orlando and C. Paar, "A scalable GF(P) elliptic curve processor archi- tecture for programmable hardware," in Proc. Workshop Cryptograph. Hardware Embed. Syst. LNCS, 2001, pp. 348–363.
  7. S. B. Ors, L. Batina, B. Preneel, and J. Vandewalle, "Hardware imple- mentation of an elliptic curve processor over GF(P) ," in Proc. IEEE Appl.-Specific Syst. Arch. Process., Jun. 2003, pp. 433–443.
  8. N. Guillermin, "A high speed coprocessor for elliptic curve scalar multiplications over Fp ," in Proc. CHES 12th Int. Conf. Cryptograph. Hardware Embed. Syst., 2010, pp. 48–64.
  9. S. Kawamura, M. Koike, F. Sano, and A. Shimbo, Cox Rower Architec- ture for Fast Parallel Montgomery Multiplication. New York: Springer- Verlag, 2000, pp. 523–538.
  10. J. C. Bajard, M. Kaihara, and T. Plantard, "Selected RNS bases for modular multiplication," in Proc. IEEE 19th Int. Symp. Comput. Arith., Jun. 2009, pp. 25–32.

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Published

2017-02-28

Issue

Section

Research Articles

How to Cite

[1]
P. Arun Kumar, C. Yamunarani, " Low-Power and Area Efficient Dual Dynamic Node Pulsed Hybrid Flip-Flop , International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 1, pp.471-475, January-February-2017.