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A Study on Conventional SRAM and Adiabatic SRAM


J. Dhanasekar, Dr. V. K. Sudha, Rinu Johnson
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Semiconductor memory is an electronic data storage device, often used as computer memory, implemented on a semiconductor-based integrated circuit. It is made in many different types and technologies. Most modern semiconductor memory devices are implemented allowing random access, which means that it takes the same amount of time to access any memory location, so data can be efficiently accessed in any random order. Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each bit. It consists of 6 Transistors in the form of cross coupled inverters. This storage cell has two stable states which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. In CMOS circuits there is short circuit power dissipation so there exist path directly from VDD to ground, hence leading to short circuit current. This drawback can be overcome by adiabatic technique. The tool used to obtain the results is Tanner EDA tool. The power obtained for the conventional SRAM is 2.2mW and for proposed adiabatic technique is 0.3mW

J. Dhanasekar, Dr. V. K. Sudha, Rinu Johnson

Complementary Metal–Oxide–Semiconductor (CMOS), Static Random Access Memory (SRAM)

  1. M. Durgadevi, R.Lavanya “Design of Low Power SRAM using Adiabatic Change of Wordline Voltage”, International Journal of Computer applications(0975-8887), 2015.
  2. Mr. Sunil Jadav , Mr. Vikrant , Dr. Munish Vashisath,” Design and Performance Analysis of Ultra Low Power 6t SRAM Using Adiabatic Technique” International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.3, June 2012.
  3. Mohammad, B.S. ; Dept. of Electr. & Comput. Eng., Khalifa Univ. of Sci., Technol. & Res., Abu Dhabi, United Arab Emirates ; Saleh, H. ; Ismail,M ”Design Methodologies for Yield Enhancement and Power Efficiency in SRAM-Based SoCs”, IEEE Trans. Very Large Scale Integration. (VLSI) Syst. , vol. 23, no. 10, October 2015.
  4. Kvatinsky, S. ; Dept. of Electr. Eng., Technion - Israel Inst. of Technol., Haifa, Israel ; Satat, G. ; Wald, N. ; Friedman, E.G. “Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies”, IEEE Trans. Very Large Scale Integration. (VLSI) Syst. , vol. 22, no. 10, October 2014.
  5. Patel, R. ; Dept. of Electr. Eng. & Computer. Eng., Univ. of Rochester, Rochester, NY, USA ; Kvatinsky, S. ; Friedman, E.G. ; Kolodny, A. Multistate “Register Based on Resistive RAM”, IEEE Trans. Very Large Scale Integration. (VLSI) Syst. , vol. 23, no. 9, September 2015.
  6. Maurya, A.K. ; Electron. & Commun. Eng., Nat. Inst. of Technol., Hamirpur, India ; Kumar, G. “Adiabatic logic: Energy efficient technique for VLSI applications” 2nd International Conference onComputer and Communication Technology (ICCCT), 2011.

Publication Details

Published in : Volume 3 | Issue 1 | January-February - 2017
Date of Publication Print ISSN Online ISSN
2017-02-28 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
531-535 IJSRSET1731122   Technoscience Academy

Cite This Article

J. Dhanasekar, Dr. V. K. Sudha, Rinu Johnson, "A Study on Conventional SRAM and Adiabatic SRAM", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 1, pp.531-535, January-February-2017.
URL : http://ijsrset.com/IJSRSET1731122.php




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