This brief proposes one new algorithm called Vertical-Horizontal Binary Common Sub-expression Elimination (VHBCSE) algorithm for designing an efficient constant multiplier architecture for fixed point reconfigurable Finite Impulse Response filter. In a reconfigurable FIR filter, the coefficients can dynamically change in real time and are thus inevitable in multistandard wireless communication systems. In the proposed algorithm, the filter coefficients are first pre-analyzed using BCSE algorithm to avoid complete redundancy in coefficient multiplication and then different lengths of Binary Common Sub-expression Elimination algorithms are applied in different layers of Multiplier adder tree to eliminate redundant computations for common sub-expressions in producing the multiplication result and hence reduce the hardware and power consumption. The use of carry save adders for much faster operation and the use of signed decimal format data representation make the design most appropriate for designing any order efficient reconfigurable systems. The Efficiency of the proposed design is shown by comparing ASIC and FPGA implementation results of the present design viz., power, area and speed with the best existing reconfigurable FIR filter implementations in the literature. Xilinx 9.2i ISE, MATLAB Filter Visualization tool and Cadence tool with Faraday 90nm CMOS technology library are used for the synthesizing purposes.
Reconfigurability, VHBCSE algorithm, Carry save adder, Signed decimal format data representation, Multiplier adder tree, Constant multiplier, finite impulse response filter, Multistandard system, VLSI design.
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Cite This Article
Amutha M, "An Efficient Constant Multiplier Architecture for Realizing Fixed Point Reconfigurable FIR filter", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 1, pp.252-261, January-February-2017.
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