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An Efficient Constant Multiplier Architecture for Realizing Fixed Point Reconfigurable FIR filter


Amutha M
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This brief proposes one new algorithm called Vertical-Horizontal Binary Common Sub-expression Elimination (VHBCSE) algorithm for designing an efficient constant multiplier architecture for fixed point reconfigurable Finite Impulse Response filter. In a reconfigurable FIR filter, the coefficients can dynamically change in real time and are thus inevitable in multistandard wireless communication systems. In the proposed algorithm, the filter coefficients are first pre-analyzed using BCSE algorithm to avoid complete redundancy in coefficient multiplication and then different lengths of Binary Common Sub-expression Elimination algorithms are applied in different layers of Multiplier adder tree to eliminate redundant computations for common sub-expressions in producing the multiplication result and hence reduce the hardware and power consumption. The use of carry save adders for much faster operation and the use of signed decimal format data representation make the design most appropriate for designing any order efficient reconfigurable systems. The Efficiency of the proposed design is shown by comparing ASIC and FPGA implementation results of the present design viz., power, area and speed with the best existing reconfigurable FIR filter implementations in the literature. Xilinx 9.2i ISE, MATLAB Filter Visualization tool and Cadence tool with Faraday 90nm CMOS technology library are used for the synthesizing purposes.

Amutha M

Reconfigurability, VHBCSE algorithm, Carry save adder, Signed decimal format data representation, Multiplier adder tree, Constant multiplier, finite impulse response filter, Multistandard system, VLSI design.

  1. Hentschel and G. Fettweis, "Software radio receivers,” in CDMA Techniques for Third Generation Mobile Systems. Dordrecht, The Netherlands: Kluwer Academic, 1999, pp. 257–283.
  2. L. Nunez-Yanez, T. Spiteri, and G. Vafiadis, "Multi-standard reconfigurable motion estimation processor for hybrid video codecs,” IET Comput. Digit. Tech., vol. 5, no. 2, pp. 73–85, Mar. 2011.
  3. Hwang, C. Mittelsteadt, and I. Verbauwhede, "Low power showdown: Comparison of five DSP platforms implementing an LPC speech codec,” in Proc. IEEE Int. Conf. Acoust. Speech Signal Process., Salt Lake City, UT, May 2001, pp. 1125–1128.
  4. Mehendale, S. D. Sherlekar, and G. Venkatesh, "Synthesis of multiplier-less FIR filters with minimum number of additions,” in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., 1995, pp. 668–671.
  5. Yagyu, A. Nishihara, and N. Fujii, "Fast FIR digital filter structures using minimal number of adders and its application to filter design,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci., vol. E79-A, no. 8, pp. 1120–1129, Aug. 1996.
  6. I. Hartley, "Subexpression sharing in filters using canonic signed digit multipliers,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 10, pp. 677–688, Oct. 1996.
  7. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and D. Durackova, "A new algorithm for elimination of common subexpressions,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 18, no. 1, pp. 58–68, Jan. 1999.
  8. Park and H. J. Kang, "Digital filter synthesis based on minimal signed digit representation,” in Proc. DAC, Jun. 2001, pp. 468–473.
  9. M. Peiro, E. I. Boemo, and L. Wanhammar, "Design of high-speed multiplierless filters using a nonrecursive signed common subexpression algorithm,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 3, pp. 196–203, Mar. 2002.
  10. Y. Yao, H. H. Chen, C. J. Chien, and C. T. Hsu, "A novel common subexpression-elimination method for synthesizing fixed-point FIR filters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 11, pp. 2215–2221, Nov. 2004.
  11. P. Vinod and E. M.-K. Lai, "Comparison of the horizontal and the vertical common subexpression elimination methods for realizing digital filters,” in Proc. IEEE Int. Conf. Circuits Syst., May 2005, vol. 1, pp. 496–499.
  12. Mahesh and A. P. Vinod, "New reconfigurable architectures for implementing FIR filters with low complexity,” IEEE Trans. Comput.Aided Design Integr. Circuits Syst., vol. 29, no. 2, pp. 275–288, Feb.2010.
  13. Hatai, I. Chakrabarti, and S. Banerjee, "An efficient VLSI architecture of a reconfigurable pulse-shaping FIR interpolation filter for multi-standard DUC,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., May 2014 Online]. Available: http://ieeexplore.ieee.org
  14. K. Meher, "New approach to look-up-table design and memory based realization of FIR digital filter,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 592–603, Mar. 2010.
  15. Y. Park and P. K. Meher, "Efficient FPGA and ASIC realizations of DA-based reconfigurable FIR digital filter,” IEEE Trans. Circuits Syst. II, Exp. Brief, vol. 61, no. 7, pp. 511–515, Jul. 2014.
  16. F. Hsiao, J. H. Z. Jian, and M. C. Chen, "Low-cost FIR filter designs based on faithfully rounded truncated multiple constant multiplication/ accumulation,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 60, no. 5, pp. 287–291, May 2013.
  17. H. Chang, J. Chen, and A. P. Vinod, "Information theoretic approach to complexity reduction on FIR filter design,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 8, pp. 2310–2321, Sep. 2008.
  18. Xilinx Inc. LogiCORE IP FIR Compiler v5.0, San Jose, CA, 2010 Online]. Available: http://www.xilinx.com
  19. R. Mahesh and A. P. Vinod, "A new common subexpression elimination algorithm for realizing low-complexity higher order digital filters,” IEEE Trans. Comput. Aided Design Integr. Circuits Syst., vol. 27, no. 2, pp. 217–229, Feb. 2008.

Publication Details

Published in : Volume 3 | Issue 1 | January-February - 2017
Date of Publication Print ISSN Online ISSN
2017-02-28 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
252-261 IJSRSET173143   Technoscience Academy

Cite This Article

Amutha M, "An Efficient Constant Multiplier Architecture for Realizing Fixed Point Reconfigurable FIR filter", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 1, pp.252-261, January-February-2017.
URL : http://ijsrset.com/IJSRSET173143.php




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