IJSRSET calls volunteers interested to contribute towards the scientific development in the field of Science, Engineering and Technology

Home > IJSRSET173182                                                     


Power Efficient Memory Design using MTCMOS Technique in 30nm Technology

Authors(2):

P. Kaviya Priya, T. Shanmugaraja
  • Abstract
  • Authors
  • Keywords
  • References
  • Details
Sense amplifiers play an important role in memories like Dynamic Random Access and Static Random Access memories. A sense amplifier compares the bit line voltage and its complement amplifies it to rail to rail output voltages. This paper mainly concentrated on the design of low power sense amplifier. An analytical model of different sense amplifier has been derived and simulated using 30nm CMOS (Complementary metal oxide semiconductor) technology with variable supply voltage using MTCMOS (Multi Threshold CMOS) technique. MTCMOS is an effective circuit level technique that improves the performance and design low power cell by utilizing both low and high threshold voltage transistors. The conventional voltage latch sense amplifier designed using MTCMOS technique to perform better in terms of power dissipation is proposed in this paper using SYNOPSYS EDA tool.

P. Kaviya Priya, T. Shanmugaraja

Memory, Sense Amplifier, Low Power, MTCMOS.

  1. AlirezaShafaei, Yanzhi Wang, Antonio Petraglia, and MassoudPedram.October 2012.Design Optimization of Sense Amplifiers using Deeply-scaled FinFET Devices. IJCST Volume. 40, Issue 1.
  2. Birinderjit Singh Kalyan, AmitVerma, Inderpreet Kaur, IqbaldeepKaur. September 2010 .Low Power High Speed Current Sense Amplifier , IJCST Volume.1, Issue 1.
  3. Fabian KHATEB, Salma BAY ABO DABBOUS ,Spyridon Vlassis.A Survey of Non-conventional Techniques for Low- voltage Low-power Analog Circuit.
  4. A, Vivek.K, Vaijayanthi.M,Sabeetha.S.January 2014 Implementation of latch type sense amplifier. International Journal of Research in Engineering and Technology.
  5. Hinamalviya,SudhaNayar,C.M Roy.May 2013. A new approach for Leakage Power Reduction Techniques in Deep Submicron Technologies in CMOS circuit for VLSI Applications.International Journal of Advanced Research in Computer Science and Software Engineering,Volume.3, Issue 5.
  6. Jyotihooda, Saritaola, Manishasaini. April 2013. Design and Analysis of a Low Power Sense Amplifier for Memory Application, International Journal of Innovative Technology and Exploring Engineering (IJITEE) ,Volume.2, Issue-5.
  7. Manish Kumar.2015.Realization of ultra low voltage circuit design for internet of things.Jounals of Electronic devices,Volume.21.
  8. Priyanka Singh Yadav,Varun Kumar Pandey.May 2015. Power Efficiency of Half Adder design using MTCMOS Technique in 35nm regime.IJIRST –International Journal for Innovative Research in Science &Technology,Volume.1 ,Issue 12.
  9. Parita Patel, SameenaZafar, and HemantSoni.April 2014. Performance of Various Sense Amplifier Topologies in sub100nm Planar MOSFET Technology.International Journal of EmergingTrends & Technology in Computer Science (IJETTCS),Volume.3, Issue 2.
  10. Parita Patel, SameenaZafar,and Hemantsoni.May 2014. Process Variation Induced Mismatch Analysis In Sense Amplifiers. International Journal of Research in Computer and Communication Technology, Volume.3, Issue 5.
  11. Ravi Dutt, Mr. Abhijeet,April 2012. High Speed Current Mode Sense Amplifier for SRAM Applications.IOSR Journal of Engineering, Volume.2(5).
  12. S.Reniwal and S.K.Vishvakarma. March 2013. A Reliable, Process-Sensitive-Tolerant Hybrid Sense Amplifier for Ultralow Power RAM. International Journal of Electronics and Electrical Engineering Volume.1, No. 1.
  13. E et al.,2010. Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM, IEEE JSSC, Volume.26, no.4,pp. 525- 536.
  14. Weisheng Zhao, Claude Chappert, VirgileJaverliac, and Jean- Pierre Nozière.October 2012.High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits,IEEE transactions on magnetics, Volume. 45, no. 10.
  15. Zikui We, XiaohongPengl, JinhuiWangl.HaibinYinl, Na Gonl.April 2011.Novel cmossram voltage latched sense amplifiers design based on 65 nm technology International Journal of Innovative Technology and Exploring Engineering (IJITEE) ,Volume.4, Issue-1.

Publication Details

Published in : Volume 3 | Issue 1 | January-February - 2017
Date of Publication Print ISSN Online ISSN
2017-02-28 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
333-337 IJSRSET173182   Technoscience Academy

Cite This Article

P. Kaviya Priya, T. Shanmugaraja, "Power Efficient Memory Design using MTCMOS Technique in 30nm Technology", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 1, pp.333-337, January-February-2017.
URL : http://ijsrset.com/IJSRSET173182.php