Design and Analysis of Johnson Counter Based on DFAL Technique

Authors

  • Veena Battula  Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, SSITM, Bhilai, India
  • Vishal Moyal  Department of Electronics & Telecommunication, Shri Shankaracharya Technical Campus, SSITM, Bhilai, India

Keywords:

DFAL, Johnson Counter, CADENCE VIRTUOSO, CMOS

Abstract

In VLSI design,low power dissipation and high speed are the prime concern now a days.This paper presents a diode free adiabatic logic (DFAL) based Johnson Counter. The performance parameters interms of power dissipation, time delay and PDP of the DFAL based circuit are compared with its conventional CMOS counterpart which shows improved performance,without adding circuit complexity and energy saving of 30% is achieved.The design has been carried out on CADENCE VIRTUOSO SPECTRE simulator and is implemented at?90nm CMOS technology

References

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2017-06-30

Issue

Volume 3, Issue 3, May-June-2017

Section

Research Articles

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Veena Battula, Vishal Moyal, " Design and Analysis of Johnson Counter Based on DFAL Technique, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 3, pp.327-332 , May-June-2017.