Low-Latency Communication Architecture For MACS

Authors(6) :-Bhagyamma S, Neelappa, Rajesha K S, Shashikanth N S, Ranjitha B C, Anuradha K S

To enhance the parallelism and system scalability for single chip VLSI design, NoC’s are used and they are increasing day by day. In this paper we proposed MACS architecture which provides low latency, flexibility and scalability using a circuit switching technique. MACS enhances their inter processing element communication to maximize bandwidth utilization. The proposed architecture has been verified and tested on FPGA board and the results revels that the proposed architecture has better performance in terms of speed and power with compromising the area. The FPGA implementation of MACS requires 440 slices with frequency of 152.09MHz and power consumption of 0.457W.

Authors and Affiliations

Bhagyamma S
Department of Electronics & Communication Engineering, GEC, Kushalnagar, Kodagu, Karnataka, India
Neelappa
Department of Electronics & Communication Engineering, GEC, Kushalnagar, Kodagu, Karnataka, India
Rajesha K S
Department of Electronics & Communication Engineering, GEC, Kushalnagar, Kodagu, Karnataka, India
Shashikanth N S
Department of Electronics & Communication Engineering, GEC, Kushalnagar, Kodagu, Karnataka, India
Ranjitha B C
Department of Electronics & Communication Engineering, GEC, Kushalnagar, Kodagu, Karnataka, India
Anuradha K S
Department of Electronics & Communication Engineering, GEC, Kushalnagar, Kodagu, Karnataka, India

NoC, minimal adaptive, distributed round-robin, FPGA, HDL

  1. Wiklund-liu, switched network on chip for hard real time embedded systems, IEEE Computer Society, 2003, p.8.
  2. Bobda-ali, Dynamic interconnection of reconfigurable modules on reconfigurable devices, IEEE Des. Test comput., Vol.22, No.5, pp.443-451, 2005.
  3. E Carara, N Calazans, F Mores, A new router architecture for high-performance intrachip networks, J. Integrated Circuits Syst., Vol.3, No.1, pp.23-31, 2008.
  4. A. Jara-Berrocal and A. Gordon-Ross, SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems, in Proc. Des., Autom. Test Eur. Conf., 2009, pp. 268-273.
  5. J. Lin and X. Lin, Express circuit switching: Improving the performance of bufferless networks on-chip, in Proc. IEEE First Int. Conf. Network Comput., Nov. 2010, pp. 162-166.
  6. AK Lusala and JD Legat, A sdm-tdm based circuit-switched router for on-chip networks, in Proc. Reconfigurable Commun.- centric Systems-on-Chip 6th Int. Workshop, Jun. 2011, pp. 1-8.
  7. N Teimouri, M Modarressi, Power and performance efficient partial circuits in packet-switched networks-on-chip, in Proc. IEEE 21st Euromicro Int. Conf. Parallel, Distrib. Netw. Process, Feb. 2013, pp. 509-513.
  8. Marta Ort n-Obn, DaroSurez-Gracia, Analysis of network-on-chip topologies for cost-efficient chip multiprocessors, microprocessors and Microsystems,5 feb 2016,pp:1-13.
  9. Rohith Kumar, Gordon Ross, MACS: A highly customizable low-latency communication architecture, Vol.27, No.1, 2016.

Publication Details

Published in : Volume 3 | Issue 3 | May-June 2017
Date of Publication : 2017-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 333-343
Manuscript Number : IJSRSET173365
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Bhagyamma S, Neelappa, Rajesha K S, Shashikanth N S, Ranjitha B C, Anuradha K S, " Low-Latency Communication Architecture For MACS, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 3, pp.333-343, May-June-2017.
Journal URL : http://ijsrset.com/IJSRSET173365

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