An Efficient Architecture for Double Precision Floating Point Adder with LOA

Authors

  • S. Rajasekhar Reddy  M.Tech Scholar, ECE Department, CIET, Guntur, Andhra Pradesh, India
  • M. Kalapana Chowdary  Assistant. Professor, ECE Department, CIET, Guntur, Andhra Pradesh, India
  • P. Kanvitha  M.Tech Scholar, ECE Department, CIET, Guntur, Andhra Pradesh, India

Keywords:

Double Precision, Floating-Point Adders, Area Efficient.

Abstract

Because of dynamic representation capabilities and a large spectrum of numbers can be represented with a limited number of bits, floating-point numbers are being widely adopted in the fields of scientific applications. A floating-point arithmetic unit is specifically designed to carry out on floating-point numbers and is one of the most common parts of any computing system in the area of binary applications. Floating-point additions are the most frequent floating-point operations and floating-point adders are therefore critically important components in signal processing and embedded platforms. This review paper presents the survey of related works of different algorithms/techniques which are important for implementation of double precision floating point adder with reduced delay based on FPGAs. In this paper, an area and delay efficient floating-point adder are proposed by approximately designing an exponent subtractor and mantissa adder. Related operations such as normalization and rounding are also dealt with in terms of inexact computing.

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Published

2017-08-31

Issue

Section

Research Articles

How to Cite

[1]
S. Rajasekhar Reddy, M. Kalapana Chowdary, P. Kanvitha, " An Efficient Architecture for Double Precision Floating Point Adder with LOA, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 5, pp.551-555, July-August-2017.