Implementation of FPGA based Encoding schemes for NoC

Authors

  • Neelappa  Government Engineering College Engineering Kushalnagar, Karnataka, India

Keywords:

ECC, HDL, FPGA

Abstract

As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NIs). In this paper, we present a set of data encoding schemes aimed at reducing the utilization of the area and delay of the links of an NoC. The proposed different data encoding schemes are simulated and implemented on FPGA board.

References

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2017-08-31

Issue

Volume 3, Issue 5, July-August-2017

Section

Research Articles

License

Copyright (c) IJSRSET

Creative Commons License

This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
Neelappa, " Implementation of FPGA based Encoding schemes for NoC, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 5, pp.173-178, July-August-2017.