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Implementation of FPGA based Encoding schemes for NoC

Authors(1):

Neelappa
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As technology shrinks, the power dissipated by the links of a network-on-chip (NoC) starts to compete with the power dissipated by the other elements of the communication subsystem, namely, the routers and the network interfaces (NIs). In this paper, we present a set of data encoding schemes aimed at reducing the utilization of the area and delay of the links of an NoC. The proposed different data encoding schemes are simulated and implemented on FPGA board.

Neelappa

ECC, HDL, FPGA

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Publication Details

Published in : Volume 3 | Issue 5 | July-August - 2017
Date of Publication Print ISSN Online ISSN
2017-08-31 2395-1990 2394-4099
Page(s) Manuscript Number   Publisher
173-178 IJSRSET173424   Technoscience Academy

Cite This Article

Neelappa, "Implementation of FPGA based Encoding schemes for NoC", International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 5, pp.173-178, July-August-2017.
URL : http://ijsrset.com/IJSRSET173424.php