Design of Non-Volatile Cache Memory Using Spin Orbit Torque MRAM and Schottky Diode

Abstract

The cache memory design by using Spin Orbit Torque (SOT)-Magnetic (or Magneto-resistive) Random Access Memory (or) MRAM is a next generation developing and promising technology. This SOT-MRAM with schottky diode offers too many benefits such as non-volatility nature, small in size, higher density, low power consumption, scalability and infinite times of endurance. In this project, we provide an exhaustive evaluation of SOT-MRAM with schottky diode at both logic-level and layout-level in terms of size, performance, complexity and energy related parameters and compare them with the existing other cache memory technologies. The designed architecture at layout-level analysis shows that proposed SOT MRAM with schottky diode (using for the L1 & L2-Data-cache and L1& L2-Instruction-cache) will decreases the size by 83.3% and 46.7%, energy consumption reduced by 11.68x and 0.013x and achieve the similar write-read speed compared to an SRAM-only and existing SOT MRAM con?guration. Furthermore, the data retention failure chance of proposed SOT-MRAM is 27x lesser than the probability of radiation-induced soft errors in SRAM, for a 90nm technology. All of these benefits will make the SOT-MRAM with schottky diode a viable choice for processor cache memory.