Design of Radix-8 Mbe-Multiplier Based on Efficient Parallel Multiplier Accumulator

Authors(3) :-C V Madhu Kumar, G N Kodanda Ramaiah, K Rasadurai

The parallel multiplier-accumulator based radix-8 modified booth recorder is a very promising and emerging multiplication technology because of its various benefits like high density thanks to less no of execution blocks, low power dissipation and nice performance speed. During this projected project an innovative design of multiplier-and-accumulator (MAC) is employed for top speed and low-power style and it's achieved by mistreatment the renewed adder and modified booth encoder technique. This recommended multiplier 16-bit modified booth encoder design fortified with SPST adder is controlled by a general AND logic data detection unit. This booth modified algorithm encoder will persistently reduce the generating partial-products logic blocks by a number factor of 2. This novel designed SPST hybrid carry save adder (CSA) saves the generated carry and so parallel multiplication is done without waiting for carry from LSB carry, it reduce the quantity of bits in the last adder which will avoids the excessive addition and consequently minimize the switch power dissipation, and conjointly thanks to an occasional low power fitted with performance enhanced carry select adder (CSA) logic circuit. The front end design VLSI tool Xilinx-ISE v14 simulator is used for logical verification, and Xilinx-ISE v14 tool for further synthesizing and performing placing execution blocks & wire routing operation for system verification on targeted FPGA. This proposed multiplier time taken to execute 2x16-bit multiplication operation and time to produce 32-bit output is typically high speeder then all existing designs.

Authors and Affiliations

C V Madhu Kumar
M.Tech student, Department of ECE-VLSI, Kuppam Engineering College, Kuppam, Andhra Pradesh, India
G N Kodanda Ramaiah
HOD & Professor, Department of ECE, Kuppam Engineering College, Kuppam, Andhra Pradesh, India
K Rasadurai
Professor, Department of ECE, Kuppam Engineering College, Kuppam, Andhra Pradesh, India

Modified Booth Encoder, Carry Select Adder, Multiplier-And-Accumulator, Booth Recorder, Low Power, Radix-Eight, High Speed.

  1. A Amaricai, M. Vladutiu, and O. Boncalo, "Design issues and implementations for floating-point divide add fused," IEEE Trans. Circuits Syst. II-Exp. Briefs, vol. 57, no. 4, pp. 295-299, Apr. 2010.
  2. E E. Swartzlander and H. H. M. Saleh, "FFT implementation with fused floating-point operations," IEEE Trans. Comput., vol. 61, no. 2, pp. 284-288, Feb. 2012.
  3. J J. F. Cavanagh, Digital Computer Arithmetic. New York: McGraw- Hill, 1984.
  4. S Nikolaidis, E. Karaolis, and E. D. KyriakisBitzaros, "Estimation of signal transition activity in FIR filters implemented by a MAC architecture," IEEE Trans. Comput.Aided Des. Integr. Circuits Syst., vol. 19, no. 1, pp. 164-169, Jan. 2000.
  5. O Kwon, K. Nowak, and E. E. Swartzlander, "A 16-bit by 16-bitMAC design using fast 5: 3 compressor cells," J. VLSI Signal Process. Syst., vol. 31, no. 2, pp. 77-89, Jun. 2002.
  6. L-H. Chen, O. T.-C. Chen, T.-Y.Wang, and Y.C. Ma, "A multiplication- accumulation computation unit with optimized compressors and minimized switching activities," in Proc. IEEE Int, Symp. Circuits and Syst., Kobe, Japan, 2005, vol. 6, pp. 6118-6121.
  7. Y-H. Seo and D.-W. Kim, "A new VLSI architecture of parallel multiplier-accumulator based on Radix-2 modified Booth algorithm," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 2, pp. 201-208, Feb. 2010.
  8. APeymandoust and G. de Micheli,"Using Symbolic algebra in algorithmic level DSP synthesis,"in Proc.Design Automation Conf.,Las Vegas,NV,2001,pp.277282.
  9. W-C.Yeh and C.-W.Jen,"High-speed and low power split-radix FFT,"IEEE Trans.Signal Process.,vol 51,no. 3,pp.864-874,Mar.2003.
  10. C. N. Lyu and D. W. Matula," Redundant binary booth recoding, in Proc. 12th Symp. Computer. Arithmetic, 1995, pp. 50-57.

Publication Details

Published in : Volume 4 | Issue 10 | September-October 2018
Date of Publication : 2018-10-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 290-297
Manuscript Number : IJSRSET1841013
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

C V Madhu Kumar, G N Kodanda Ramaiah, K Rasadurai, " Design of Radix-8 Mbe-Multiplier Based on Efficient Parallel Multiplier Accumulator, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 10, pp.290-297, September-October-2018. Available at doi : https://doi.org/10.32628/18410IJSRSET
Journal URL : http://ijsrset.com/IJSRSET1841013

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