BIST Schemes for Low Power High Fault Test Pattern Generation

Authors(2) :-M. Pavithra Jyothi, Dr. C. RamSingla

BIST is a viable approach to test today's digital systems. During self-test, the switching activity of the Circuit under Test (CUT) is significantly increased compared to normal operation and leads to an increased power consumption which often exceeds specified limits. The proposed method generates Multiple Single Input Change (MSIC) vectors in a pattern. The each generated vectors are applied to a scan chain is an SIC vector. A class of minimum transition sequences is generated by the use of a reconfigurable Johnson counter and a scalable SIC counters. The proposed TPG method is flexible to both the test-per-scan schemes and the test-per-clock. A theory is also developed to represent and analyze the sequences and to extract a class of MSIC sequences. The proposed BIST TPG decreases transitions that occur at scan inputs during scan shift operations and hence reduces switching activity in the CUT. As the switching activity is reduced, the power consumption of the circuit will also be reduced.

Authors and Affiliations

M. Pavithra Jyothi
Research Scholar, SUNRISE University, Alwar, Rajasthan, India
Dr. C. RamSingla
Professor ,Dept of ECE, SUNRISE University, Alwar, Rajasthan, India

Built-in self-test (BIST), Circuit Under Test (CUT), Low Power, Single-Input Change (SIC), Test Pattern Generator (TPG), Linear Feedback Shift Register (LFSR).

  1. Y. Zorian, -A distributed BIST control scheme for complex VLSI devices, in 11th Annu. IEEE VLSI Test Symp. Dig. Papers, Apr. 1993, pp. 4-9.
  2. P. Girard, -Survey of low-power testing of VLSI circuits, IEEE Design Test Comput., vol. 19, no. 3, pp. 80-90, May-Jun. 2002.
  3. A. Abu-Issa and S. Quigley, -Bit-swapping LFSR and scan-chain ordering: A novel technique for peak- and average-power reduction in scan-based BIST, IEEE Trans. Comput.- Aided Design Integr. Circuits Syst., vol. 28, no. 5, pp. 755-759, May 2009.
  4. P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, J. Figueras, S. Manich, P. Teixeira, and M. Santos, -Low-energy BIST design: Impact of the LFSR TPG parameters on the weighted switching activity, in Proc. IEEE Int. Symp. Circuits Syst., vol.1. Jul. 1999, pp. 110-113.
  5. S. Wang and S. Gupta, -DS-LFSR:  A BIST TPG for low switching activity,  IEEE Trans. Comput.-Aided Design Integr.Circuits Syst., vol. 21, no. 7, pp. 842-851, Jul. 2002.
  6. F. Corno, M. Rebaudengo, M. Reorda, G. Squillero,  and M. Violante,  -Low  power BIST via non-linear hybrid  cellular automata, in Proc. 18th IEEE VLSI Test Symp., Apr.-May 2000, pp. 29-34.
  7. P. Girard, L. Guiller, C. Landrault, S. Pravossoudovitch, and H. Wunderlich, -A modified clock scheme for a low power BIST test pattern generator, in Proc. 19th IEEE VTS VLSI Test Symp., Mar.-Apr. 2001, pp. 306-311.
  8. D. Gizopoulos, N. Krantitis, A. Paschalis, M. Psarakis, and Y. Zorian, -Low power/energy BIST scheme for datapaths, in Proc. 18th IEEE VLSI Test Symp., Apr.-May 2000, pp. 23-28.
  9. Y. Bonhomme, P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, -A gated clock scheme for low power scan testing of logic ICs or embedded cores, in Proc. 10th Asian Test Symp., Nov. 2001, pp. 253-258.
  10. C. Laoudias and D. Nikolos, -A new test pattern generator for high defect coverage in a BIST environment, in Proc. 14th ACM Great Lakes Symp. VLSI, Apr. 2004, pp. 417-420.
  11. S. Bhunia, H. Mahmoodi, D. Ghosh, S. Mukhopadhyay, and K. Roy, -Low-power scan design using first-level supply gating, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol.13, no. 3, pp. 384-395, Mar. 2005.
  12. X. Kavousianos, D. Bakalis, and D. Nikolos, -Efficient partial scan cell gating for low-power scan-based testing, ACM Trans. Design Autom. Electron. Syst., vol. 14, no. 2, pp. 28-1-28-15, Mar. 2009.
  13. P. Girard, L. Guiller, C. Landrault, and S. Pravossoudovitch, -A test vector inhibiting technique for low energy BIST design, in Proc. 17th IEEE VLSI Test Symp., Apr. 1999, pp.407-412.
  14. S. Manich, A. Gabarro, M. Lopez, J. Figueras, P. Girard, L.   Guiller, C. Landrault, S. Pravossoudovitch, P. Teixeira, and M. Santos, -Low power BIST by filtering non-detecting vectors, Aided Design Integr. Circuits Syst., vol. 28, no. 5, pp. 755-759, May 2009.

Publication Details

Published in : Volume 3 | Issue 3 | May-June 2017
Date of Publication : 2017-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 721-727
Manuscript Number : IJSRSET1841186
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

M. Pavithra Jyothi, Dr. C. RamSingla, " BIST Schemes for Low Power High Fault Test Pattern Generation, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 3, Issue 3, pp.721-727, May-June-2017.
Journal URL : http://ijsrset.com/IJSRSET1841186

Follow Us

Contact Us