A Novel Design And Implementation Of Dual Use Of Power Lines For Design-For-Testability by using LOC and LOS Technique

Authors

  • Mahalakshmi  M. Tech Student, Department of ECE, Vemu Institute of Technical Education, Tirupathi, India
  • R. Mallikarjuna Reddy   Assistant Professor, Department of ECE, Vemu Institute of Technical Education, Tirupathi, India

Keywords:

Design-for-testability (DFT), PLC at ICs, PLC receiver, power line communications (PLCs), LOC and LOS.

Abstract

The PLC is one in which the power pins and the power distribution networks of ICs are used for data communication as well as power delivery. PLC is used in order to reduce the number of input pins that an IC needs to couple the test data signals to each and every node. Hence to extract the test data signals from this power lines, so many receivers are in need at each and every nodes of the ICs or at places where we have to apply the test. For this purpose, PLC receivers are already designed. But all of them consume very high power. So, in this paper Launch On Capture (LOC) And Launch On Shift (LOS) a power efficient CMOS PLC receiver for the same purpose in 180 nm CMOS technology under a supply voltage of 1.8 V is designed with the help of Tanner tool. To achieve this much extreme low power, so many CMOS low power technics are successfully employed like the stacking method, resistor less approach

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2018-02-28

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Volume 4, Issue 1, January-February-2018

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Research Articles

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How to Cite

[1]
Mahalakshmi, R. Mallikarjuna Reddy , " A Novel Design And Implementation Of Dual Use Of Power Lines For Design-For-Testability by using LOC and LOS Technique, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 1, pp.1288-1297, January-February-2018.