Comparative Analysis of Ladner-Fischer Adder and Han-Carlson Adder Parallel-Prefix Adder for Their Area, Delay and Power Consumption

Abstract

Parallel Prefix adders have been one of the most notable among more than a few designs proposed in the past. Parallel Prefix adders (PPA) are family of adders derived from the generally known carry look ahead adders. The need for a Parallel Prefix adder is that it is mostly fast when compared with ripple carry adders. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, and fan-out and interconnect count of logic circuits. In this paper, a comparison of two 8-bit parallel-Prefix adders (Ladner-Fischer adder and Han-Carlson adder) in their area, delay, power is proposed. In this proposed system Ladner-Fischer adder and Han-Carlson adder parallel prefix adder are used for comparison. The results reveal that the proposed Han-Carlson adder Parallel-Prefix Adder is more competent than Ladner-Fischer Parallel-Prefix adder in terms of area, delay & power. Simulation results are compared and verified using Xilinx 8.1i software.