Dynamic Dispatch Scheduling for High Performance VLIW Architecture

Authors(2) :-R. Ramesh Babu, Dr. Sachin Saxena

VLIW architecture has become widespread due to the combined bene?ts of simple hardware and compiler-extracted instruction-level parallelism. However, the VLIW instruction set architecture and its hardware implementation are tightly coupled, a novel simultaneous multithreading VLIW architecture with dynamic dispatch mechanism to address the challenge of the underutilization of computing resources. The SMT technology exploits the unused instruction slots by converting the thread level parallelism to the instruction-level parallelism, improving the efficiency. On the availability of the corresponding functional units. With the dynamic dispatch mechanism, the issues instructions to functional unit at run-time rather than at compile-time, such that the issue conflicts among multiple threads are reduced significantly. The new VLIW architecture shows that it can effectively increase the processor throughput and improve the performance.

Authors and Affiliations

R. Ramesh Babu
Research Scholar, Department of ECE, Sunrise University, Alwar, Rajasthan, India
Dr. Sachin Saxena
Supervisor, Department of ECE, Sunrise University, Alwar, Rajasthan, India

VLIW, ILP, Reorder Buffer, Dynamic Dispatch

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Publication Details

Published in : Volume 2 | Issue 6 | November-December 2016
Date of Publication : 2016-12-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 770-776
Manuscript Number : IJSRSET1841244
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

R. Ramesh Babu, Dr. Sachin Saxena, " Dynamic Dispatch Scheduling for High Performance VLIW Architecture, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 2, Issue 6, pp.770-776, November-December-2016.
Journal URL : http://ijsrset.com/IJSRSET1841244

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