Complexity Reduction in Inter Layer Inter Prediction in Scalable High Efficiency Video Coding

Authors

  • M. Sravan Kumar  Assistant Professor, Tadipatri Engineering College, Tadipatri, Anantapur, India
  • B. Jyothi Priya  Assistant Professor, Tadipatri Engineering College, Tadipatri, Anantapur, India

Keywords:

H.264/AVC scalable extension (SVC), interlayer prediction, memory bandwidth, motion estimation (ME), on-chip memory, SVC.

Abstract

Memory bandwidth and on-chip memory requirements are critical issues in motion estimation (ME) implementations for video compression. The H.264/AVC scalable extension (SVC) provides variable frame rate and resolution video in a compressed digital sequence with interlayer prediction, which complicates the problems of limited memory bandwidth and onchip memory size. In this paper, an ME algorithm is proposed for the hardware encoder design of SVC that meets memory bandwidth and on-chip memory requirements. Clustered motion estimation and coding sequence reordering at macroblock and frame level processing are proposed. Compared with existing algorithms, the proposed algorithm has a 49.20% lower external memory bandwidth and reduces the on-chip memory requirement by 80.45% with video quality enhancements of up to 0.087, 0.090, 0.078, and 0.070 dB for four-layer (FullHD-HD-D1-CIF) spatial scalability, respectively.

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International Journal of Scientific Research in Science, Engineering and Technology

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Published

2018-02-28

Issue

Volume 4, Issue 1, January-February-2018

Section

Research Articles

License

Copyright (c) IJSRSET

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This work is licensed under a Creative Commons Attribution 4.0 International License.

How to Cite

[1]
M. Sravan Kumar, B. Jyothi Priya, " Complexity Reduction in Inter Layer Inter Prediction in Scalable High Efficiency Video Coding, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 1, pp.372-377, January-February-2018.