Implementation of an Efficient Reverse Compressor Multiplier and Adder Based MAC Architecture

Authors(2) :-K. Sreenath, H. Chandrasekhar

Power dissipation is recognized as a critical parameter in modern VLSI design field. To satisfy MOORE’S law and to produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary. High speed and low power Multiplier-Accumulator (MAC) units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc.The proposed MAC uses multiplier with reverse compressor design multiplier and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of MAC architecture and their implementation by Xilinx ISE 14.3 SynthesisTool. The proposed reverse compressor multiplier and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce interms of delay.

Authors and Affiliations

K. Sreenath
Mtech Student, Department of ECE, VemuInstitute of Technical Education,Tirupathi, India
H. Chandrasekhar
Associate Professor, Department of ECE, Vemu Institute of Technical Education,Tirupathi, India

Multiply Accumulate Compressor, Reversible Gates, Adder.

  1. Chang, Chip-Hong, JiangminGu, and Mingyan Zhang."Ultra low-voltage low-power CMOS 4-2 and 5-2compressors for fast arithmetic circuits." Circuits and Systems I: Regular Papers, IEEE Transactions on 51.10 (2004): 1985-1997.
  2. Tung Thanh Hoang; Sjalander, M.; Larsson-Edefors, P., "AHigh-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its ApplicationtoaDouble-Throughput MAC Unit," Circuits and Systems I:Regular Papers, IEEE Transactions on , vol.57, no.12, pp.3073,3081, Dec. 2010.
  3. Chen Ping-hua; Zhao Juan, "High-speed Parallel 32×32-b Multiplier Using a Radix-16 Booth Encoder," IntelligentInformation Technology Application Workshops, 2009.IITAW '09. Third International Symposium on , vol., no., pp.406,409, 21-22 Nov. 2009
  4. Kiwon Choi; Minkyu Song, "Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder," Circuits and Systems, 2001. ISCAS 2001. The2001 IEEE International Symposium on , vol.2, no., pp.701,704 vol. 2, 6-9 May 2001.
  5. Rajput, R.P.; Swamy, M.N.S., "High Speed Modified Booth Encoder Multiplier for Signed and Unsigned Numbers," Computer Modelling and Simulation (UKSim),2012 UKSim 14th International Conference on , vol., no., pp.649,654, 28-30 March 2012.
  6. Yangbo Wu; Weijiang Zhang; Jianping Hu, "Adiabatic 4-2 compressors for low-power multiplier," Circuits andSystems, 2005. 48th Midwest Symposium on , vol., no., pp.1473,1476 Vol. 2, 7-10 Aug. 2005.
  7. Jaina, D.; Sethi, K.; Panda, R., "Vedic Mathematics Based Multiply Accumulate Unit," Computational Intelligenceand Communication Networks (CICN), 2011 InternationalConference on, vol., no., pp.754,757, 7-9 Oct. 2011.
  8. Aliparast, Peiman, Ziaadin D. Koozehkanani, and FarhadNazari. "An Ultra High Speed Digital 4-2 Compressor in 65-nm CMOS." International Journal of Computer Theory& Engineering 5.4 (2013).
  9. N. Weste and David Harris, "CMOS VLSI Design- A Circuits & System Perspective", Pearson Education, 2008.
  10. ChandraMohan U, "Low Power Area Efficient Digital Counters", Proceedings of the 7th VLSI Design and Test Workshops, VDAT, August 2003.
  11. Narendra C P & Ravi K M Kumar, "Efficient Comparator based Sum of Absolute Differences Architecture for Digital Image Processing Applications", Foundation of Computer Science, New York, USA, International Journal ofComputer Applications, 96(4):17-24, June 2014.
  12. D. Radhakrishnan A.P. PreethySingapore "Low Power CMOS Pass Logic 4-2 Compressor for High-SpeedMultiplication",circuits and systems, 2000, Proceedings of the 43rdIEEE Midwest Symposium, pages 1296-1298.
  13. S. F. Hsiao, M.R. Jiang and J.S. Yeh, "Design of high-speedlow-power 3-2 counter and 4-2 compressor for fast multipliers,"Electronics Letters, vol. 34, no. 4, pp. 341-342, Feb. 1998
  14. M.Margala and N.G. Durdle, "Low-Power Low-Voltage 4-2Compressors for VLSI Applications," Proc. Workshop on LowPower Design, 1999.
  15. S.Veeramachanemi, K.Krishna, L.Avinash, S.R.Puppola,M.B.Srinivas, "Novel architectures for high speed and lowpower3-2, 4-2 and 5-2 compressors", IEEE Proc .Of VLSID’07,pp.324-329,2007.
  16. HimanshuThapliyal and M.B Srinivas "Novel ReversibleMultiplier Architecture Using Reversible TSG Gate"ComputerSystems & Applications, 2006 IEEE International Conference,pages 100-103.

Publication Details

Published in : Volume 4 | Issue 1 | January-February 2018
Date of Publication : 2018-02-28
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 1095-1101
Manuscript Number : IJSRSET184195
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

K. Sreenath, H. Chandrasekhar, " Implementation of an Efficient Reverse Compressor Multiplier and Adder Based MAC Architecture, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 1, pp.1095-1101, January-February-2018. Citation Detection and Elimination     |     
Journal URL : https://ijsrset.com/IJSRSET184195

Article Preview