Manuscript Number : IJSRSET184195
Implementation of an Efficient Reverse Compressor Multiplier and Adder Based MAC Architecture
Authors(2) :-K. Sreenath, H. Chandrasekhar
Power dissipation is recognized as a critical parameter in modern VLSI design field. To satisfy MOORE’S law and to produce consumer electronics goods with more backup and less weight, low power VLSI design is necessary. High speed and low power Multiplier-Accumulator (MAC) units are required for applications of digital signal processing like Fast Fourier Transform, Finite Impulse Response filters, convolution etc.The proposed MAC uses multiplier with reverse compressor design multiplier and adders as primitive building blocks for efficient application. Further, the Verilog-HDL coding of MAC architecture and their implementation by Xilinx ISE 14.3 SynthesisTool. The proposed reverse compressor multiplier and adder based architecture used to be applied to MAC unit and in comparison to the previous design MAC unit and verified that the proposed architecture have reduce interms of delay.
K. Sreenath
Multiply Accumulate Compressor, Reversible Gates, Adder.
Publication Details
Published in :
Volume 4 | Issue 1 | January-February 2018 Article Preview
Mtech Student, Department of ECE, VemuInstitute of Technical Education,Tirupathi, India
H. Chandrasekhar
Associate Professor, Department of ECE, Vemu Institute of Technical Education,Tirupathi, India
Date of Publication :
2018-02-28
License: This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) :
1095-1101
Manuscript Number :
IJSRSET184195
Publisher : Technoscience Academy
Journal URL :
https://ijsrset.com/IJSRSET184195