A Modified Partial Product Generator Using RADIX 4 to Remove ECW

Authors(2) :-Neha R. Dhodre, Prof. Sunil R. Gupta

Adders are the most important element of the arithmetic unit especially fast parallel adder. Redundant binary signed digit (RBSD) adders are designed to perform high speed arithmetic operations. Generally in a high radix modified booth encoding algorithm the partial products are reduced in multiplication process. While designing high performance multipliers a redundant binary (RB) representation can be used due to its high modularity and carry-free addition, The traditional RB multiplier requires an extra RB partial product (RBPP) row. Redundant binary representation (RBR) is a numeral system that uses more bits than needed to represent a single binary digit so that most numbers have several representation because an error-correcting word (ECW) is generated by both the radix-4 Modified Booth encoding (MBE) and the RB encoding. This results in an additional RBPP accumulation stage for the MBE multiplier. In this thesis, a new RB modified partial product generator (RBMPPG) is proposed; it removes the extra ECW therefore saves one RBPP accumulation stage. Hence the proposed work generates fewer partial product rows than a traditional RB MBE multiplier. Operation of the system over time show that the proposed work based designs considerably improve the area and power consumption when the word length of each operand in the multiplier is at least 32 bits; these reductions over previous NB multiplier designs incur in a modest delay increase (approximately 5 percent). By using the proposed RB multiplier design the power-delay product can be reduced by up to 59 percent when compared with existing RB multipliers.

Authors and Affiliations

Neha R. Dhodre
PG Scholar, Department of E &TC, JD College of Engineering and Management, Nagpur, Maharashtra, India
Prof. Sunil R. Gupta
H.O.D., Department of E & TC, JD College of Engineering and Management, Nagpur, Maharashtra, India

Redundant binary, modified Booth encoding, RB partial product generator, RB multiplier.

  1. I Koren, Computer Arithmetic Algorithms, Prentice Hall, New York, 1993.
  2. AD. Booth, A signed binary multiplication technique, Quarterly Journal of Mechanics and Applied Mathematics 4 (1951) 236–240.
  3. O.L. McSorley, High-speed arithmetic in binary computers, Proceedings of the Institute of Radio Engineers 49 (1961) 67–91.
  4. Y. Harata, Y. Nakamura, H. Nagase, M. Takigawa, N. Takagi, A high-speed multiplier using a redundant binary adder tree, IEEE Journal of Solid-State Circuits 22 (1987) 28–34.
  5. H Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, K. Mashiko, An 8.8–11 s 54 54-bit multiplier with high-speed redundant binary architecture, IEEE Journal of Solid-State Circuits 31 (1996) 773–783.
  6. SM. Yen, C.S. Laih, C.H. Chen, J.Y. Lee, An efficient redundant-binary number to binary number converter, IEEE Journal of Solid-State Circuits 27 (1992) 109–112.
  7. N Besli, R.G. Deshmukh, A novel redundant binary signed-digit (RBSD) Booth’s encoding, in: Proceedings of the IEEE Southeast Conference, Columbia, SC, 2002, pp. 426–431.
  8. N. Besli, R.G. Deshmukh, A 54 54-bit multiplier with a new redundant binary Booth’s encoding, Proceedings of the Canadian Conference on Electrical and Computer Engineering 2 (2002) 597–602 (Winnipeg, Canada).
  9. S. Lee, S. Bae, H. Park, A compact radix-64 54 54 CMOS redundant binary parallel multiplier, IEICE Transactions on Electronics E 85-C (2002) 1342–1350.
  10. Y. Kim, B. Song, J. Grosspietsch, S. Gillig, A carry-free 54 54-bit multiplier using equivalent bit conversion algorithm, IEEE Journal of Solid-State Circuits 36 (2001) 1538–1545.

Publication Details

Published in : Volume 4 | Issue 7 | March-April 2018
Date of Publication : 2018-03-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 331-334
Manuscript Number : IJSRSET1844343
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Neha R. Dhodre, Prof. Sunil R. Gupta, " A Modified Partial Product Generator Using RADIX 4 to Remove ECW, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 7, pp.331-334, March-April-2018.
Journal URL : http://ijsrset.com/IJSRSET1844343

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