Implementation of Low Power CMOS Structure Using Pass Transistor Adiabatic Logic

Authors(1) :-Dr. R. Prakash Rao

Power consumption is the important and basic parameters of any kind of digital integrated circuit (IC). There is always a tradeoff between power and performance to meet the systems requirement. System cost is directly affected by power. Adiabatic circuits are those circuits which work on the principle of adiabatic charging and discharging and which recycle the energy from output nodes instead of discharging it to ground. Conventional CMOS circuits achieve a logic 1 or logic 0 by charging the load capacitor to supply voltage Vdd and discharging it to ground respectively. All simulation result and analysis are perform on 90 nm PTM technology using Tanner tool.

Authors and Affiliations

Dr. R. Prakash Rao
Associate Professor, Electronics and Communication Engineering, Matrusri Engineering College, Saidabad, Hyderabad, India

Power and Performance, Adiabatic Circuit, Charging And Discharging, CMOS Circuits, Tanner Tool

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Publication Details

Published in : Volume 4 | Issue 8 | May-June 2018
Date of Publication : 2018-06-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 385-388
Manuscript Number : IJSRSET1848103
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Dr. R. Prakash Rao, " Implementation of Low Power CMOS Structure Using Pass Transistor Adiabatic Logic, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 8, pp.385-388, May-June-2018.
Journal URL : http://ijsrset.com/IJSRSET1848103

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