Implementation of High Speed 16x16 Vedic Multiplier using Verilog HDL Coding Technique

Authors(1) :-Choksi Vandana M

Multiplication is an operation much needed in Digital Signal Processing for various applications. This paper puts forward a high speed Vedic multiplier which is efficient in terms of speed, making use of Urdhva Tiryagbhyam, a sutra from Vedic Math for multiplication and MAC unit for performing addition of partial products and also compares it with the characteristics of existing algorithms. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. The below algorithms aids to parallel generation of partial products and faster carry generation respectively, leading to better performance. The code is written in Verilog HDL and implemented on ModelSim.

Authors and Affiliations

Choksi Vandana M
Department of E&C, FoT, Dharmsinh Desai University, Nadiad, Gujarat, India

Vedic mathematics, Urdhva triyakbhyam sutra, Vedic Multiplier

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Publication Details

Published in : Volume 4 | Issue 9 | July-August 2018
Date of Publication : 2018-07-30
License:  This work is licensed under a Creative Commons Attribution 4.0 International License.
Page(s) : 142-148
Manuscript Number : IJSRSET184933
Publisher : Technoscience Academy

Print ISSN : 2395-1990, Online ISSN : 2394-4099

Cite This Article :

Choksi Vandana M, " Implementation of High Speed 16x16 Vedic Multiplier using Verilog HDL Coding Technique, International Journal of Scientific Research in Science, Engineering and Technology(IJSRSET), Print ISSN : 2395-1990, Online ISSN : 2394-4099, Volume 4, Issue 9, pp.142-148, July-August.2018
URL : http://ijsrset.com/IJSRSET184933

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